[Bug target/80510] Optimize Power7/power8 Altivec load/stores

["meissner at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80510

--- Comment #1 from Michael Meissner <meissner at gcc dot gnu.org> ---
Author: meissner
Date: Thu May 18 19:34:13 2017
New Revision: 248254

URL: https://gcc.gnu.org/viewcvs?rev=248254&root=gcc&view=rev
Log:
[gcc]
2017-05-18  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/80510
        * config/rs6000/predicates.md (simple_offsettable_mem_operand):
        New predicate.

        * config/rs6000/rs6000.md (ALTIVEC_DFORM): New iterator.
        (define_peephole2 for Altivec d-form load): Add peepholes to catch
        cases where the register allocator uses a move and an offsettable
        memory operation to/from a FPR register on ISA 2.06/2.07.
        (define_peephole2 for Altivec d-form store): Likewise.

[gcc/testsuite]
2017-05-18  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/80510
        * gcc.target/powerpc/pr80510-1.c: New test.
        * gcc.target/powerpc/pr80510-2.c: Likewise.


Added:
    trunk/gcc/testsuite/gcc.target/powerpc/pr80510-1.c
    trunk/gcc/testsuite/gcc.target/powerpc/pr80510-2.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/rs6000/predicates.md
    trunk/gcc/config/rs6000/rs6000.md
    trunk/gcc/testsuite/ChangeLog