[Bug c/79219] Feature request: double width/single width -> single width integer division and remainder

["hpa at zytor dot com" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79219

--- Comment #4 from H. Peter Anvin <hpa at zytor dot com> ---
There are a few issues with that:

a) the overflow behavior is inherently different, which is why the inline you
propose doesn't work.  Try compiling the attached program, on x86-64 it
produces a call to __udivti3 rather than an inline div instruction (output
shown below).  The reason is that the div instruction will trap on overflow.

b) it requires algorithms to be implemented using lengthy (source-code-wise)
multi-precision to be portable between 32- and 64-bit architectures.

c) it seems likely that getting __intN where N > CHAR_BIT*sizeof(uintmax_t)
into a standard would be very hard, and thus would not be possible to
standard-track (although it could be used as an implementation on gcc using a
header inline, of course.)

dbldiv.o:     file format elf64-x86-64


Disassembly of section .text:

0000000000000000 <div2to1>:
   0:   45 31 c9                xor    %r9d,%r9d
   3:   49 89 fa                mov    %rdi,%r10
   6:   55                      push   %rbp
   7:   4c 89 cf                mov    %r9,%rdi
   a:   48 89 d1                mov    %rdx,%rcx
   d:   4c 89 d5                mov    %r10,%rbp
  10:   31 d2                   xor    %edx,%edx
  12:   48 01 f7                add    %rsi,%rdi
  15:   48 11 d5                adc    %rdx,%rbp
  18:   48 89 ca                mov    %rcx,%rdx
  1b:   31 c9                   xor    %ecx,%ecx
  1d:   48 89 ee                mov    %rbp,%rsi
  20:   e8 00 00 00 00          callq  25 <div2to1+0x25>
                        21: R_X86_64_PC32       __udivti3-0x4
  25:   5d                      pop    %rbp
  26:   c3                      retq   
  27:   66 0f 1f 84 00 00 00    nopw   0x0(%rax,%rax,1)
  2e:   00 00 

0000000000000030 <div2to1_expected>:
  30:   48 89 d1                mov    %rdx,%rcx
  33:   48 89 f0                mov    %rsi,%rax
  36:   48 89 fa                mov    %rdi,%rdx
  39:   48 f7 f2                div    %rdx
  3c:   c3                      retq