[Bug rtl-optimization/78671] [7 Regression] ICE: in extract_constrain_insn, at recog.c:2213 with -Og -march=skylake-avx512

["ubizjak at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78671

--- Comment #4 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Vladimir Makarov from comment #3)

> It has just triggered a latent bug.  It is a pretty interesting bug.  The
> problem is that a TImode pseudo has class INT_SSE_REGS and r15(44) smoothly
> goes to xmm8 (45).  So using available regs in LRA, r15 is ok for the pseudo.
> 
> Actually on machine-depended side, a more detail implementation
> HARD_REGNO_MODE_OK could solve the problem.  But it is too complicated and
> error prone and require a lot of efforts to define the macro accurately for
> all classes and modes.
On machine-dependend side, there is HARD_REGNO_NREGS macro that should be taken
into account when allocating modes that live in multiple registers. This macro
returns 2 for r15 in TImode. There is no r16 available, so r15 should be
rejected as a TImode register from the beginning.