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[Bug rtl-optimization/78526] [7 Regression] ICE: in decompose, at rtl.h:2117 with -g -mavx512bw
- From: "jakub at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Fri, 25 Nov 2016 14:14:13 +0000
- Subject: [Bug rtl-optimization/78526] [7 Regression] ICE: in decompose, at rtl.h:2117 with -g -mavx512bw
- Auto-submitted: auto-generated
- References: <bug-78526-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78526
--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
What happens is that valtrack creates a paradoxical subreg:
(debug_insn 28 14 15 2 (var_location:V4TI D#2 (subreg:V4TI (reg:TI 94) 0)) -1
(nil))
(insn 15 28 16 2 (set (subreg:TI (reg/v:V4TI 90 [ v ]) 0)
(reg:TI 94)) "pr78526.c":8 80 {*movti_internal}
(expr_list:REG_DEAD (reg:TI 94)
(nil)))
during cse1 - with the meaning that nothing is known about the other elements
of the vector v, only about the first element.
But then simplify-rtx.c has bogus handling of CONST_WIDE_INT.
Though I'd say at least for debug info purposes we should be careful about
paradoxical subregs, because they mean the upper bits are not really defined
rather than zero or the value sign or zero extended.