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[Bug target/78012] -mfpxx produces assembly code using odd FP registers on MIPS
- From: "macro at linux-mips dot org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Wed, 23 Nov 2016 19:57:49 +0000
- Subject: [Bug target/78012] -mfpxx produces assembly code using odd FP registers on MIPS
- Auto-submitted: auto-generated
- References: <bug-78012-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78012
Maciej W. Rozycki <macro@linux-mips.org> changed:
What |Removed |Added
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CC| |matthew.fortune at imgtec dot com
--- Comment #5 from Maciej W. Rozycki <macro@linux-mips.org> ---
I have been able to reproduce the bug now -- to trigger it you need to
request classic SVR4 code either by means of compiler defaults or with
the use of the `-mplt' option, in which case a pair of single-word FPU
accesses is produced for $f15: first SWC1 to save it, and then LWC1 to
restore it from the stack frame, as follows:
swc1 $f15,224($sp) # 1178 *movsi_internal/15 [length = 4]
lwc1 $f15,224($sp) # 1179 *movsi_internal/13 [length = 4]
Notice the integer mode used. I haven't investigated it further.
You need all of `-mips32r2 -mfpxx -mno-plt' to trigger it. It does
*not* trigger if `-fPIC' or `-fPIE' is used in place of `-mno-plt'.