[Bug target/77686] [6/7 Regression] wrong code on arm-linux-gnueabi and arm-linux-gnueabihf

["ktkachov at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77686

ktkachov at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|kyrylo.tkachov at arm dot com      |

--- Comment #7 from ktkachov at gcc dot gnu.org ---
As snippet of the assembly output without scheduling (-fno-schedule-insns2):
.LEHE0:
        add     r3, sp, #32
        str     r5, [sp, #32] <-------- I1
        add     ip, sp, #8
        str     r5, [sp, #36] <-------- I2
        add     r4, sp, #16
        ldm     r3, {r0, r1}  <---------I3
        add     lr, sp, #4
        str     r5, [sp, #16]
        mov     r2, #3
        str     lr, [sp, #20]
        movw    r5, #:lower16:<sym>
        stm     ip, {r0, r1}
        movt    r5, #:upper16:<sym>
        ldm     r4, {r0, r1}
        movw    lr, #:lower16:<sym>
        str     r5, [sp, #40]
        <snip>

The same region with scheduling:
.LEHE0:
        add     r3, sp, #32
        add     ip, sp, #8
        add     r4, sp, #16
        ldm     r3, {r0, r1} <---------- I3
        add     lr, sp, #4
        str     r5, [sp, #16]
        mov     r2, #3
        str     lr, [sp, #20]
        movw    lr, #:lower16:<sym>
        stm     ip, {r0, r1}
        movt    lr, #:upper16:<sym>
        ldm     r4, {r0, r1}
        str     r5, [sp, #32] <---------- I1
        str     r5, [sp, #36] <---------- I2

The stores I1 and I2 were moved past the load I3 that loads from SP + 32
If I manually move those two stores back before I3 the program doesn't abort