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[Bug target/77405] SIGBUS from gnatmake in stage 3 (gcc 7.0)
- From: "hjl.tools at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Fri, 02 Sep 2016 14:49:07 +0000
- Subject: [Bug target/77405] SIGBUS from gnatmake in stage 3 (gcc 7.0)
- Auto-submitted: auto-generated
- References: <bug-77405-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77405
H.J. Lu <hjl.tools at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |WAITING
CC|hjl at gcc dot gnu.org |hjl.tools at gmail dot com
--- Comment #14 from H.J. Lu <hjl.tools at gmail dot com> ---
(In reply to Eric Botcazou from comment #11)
> > * config/i386/i386.h (MOVE_MAX_PIECES): Use TImode in 64-bit
> > mode if unaligned SSE load and store are optimal.
>
> Then the SIGBUS is trigged by an SSE intruction operating on unaligned
> memory and I presume that the kernel doesn't patch things up, unlike on
> Linux?
Linux x86 kernel doesn't patch unaligned load/store. GCC should generate
unaligned load/store instructions when memory is misaligned. Why does
GCC think memory is aligned when it is not. Is this misaligned memory
on stack? Please show the instruction where SIGBUS happened.