[Bug rtl-optimization/71976] [avr] insn-combiner deletes a live 64-bit shift

["gjl at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71976

--- Comment #2 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
Bugzille does not allow me to attach the .combine dump (for reference).

...anyway the relevant part of the dump is:

In .242r.ud_dce there is the following right shift insn:

(insn 51 50 52 2 (set (reg:QI 16 r16)
        (const_int 40 [0x28])) bug-combin.c:29 71 {movqi_insn}
     (nil))
(insn 52 51 61 2 (set (reg:DI 18 r18)
        (ashiftrt:DI (reg:DI 18 r18)
            (reg:QI 16 r16))) bug-combin.c:29 1416 {ashrdi3_insn}
     (expr_list:REG_DEAD (reg:QI 16 r16)
        (nil)))

Insn combine tries to macht the combination of these two insns:

Trying 51 -> 52:
Failed to match this instruction:
(set (reg:DI 18 r18)
    (reg:DI 18 r18))
allowing combination of insns 51 and 52
original costs 4 + 32 = 36
replacement cost 4
deferring deletion of insn with uid = 51.
modifying insn i3    52: r18:DI=r18:DI
deferring rescan insn with uid = 52.

So the combination is wrong; for some reason the shift is transformed to a
no-op move and then removed...