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[Bug target/63359] aarch64: 32bit registers in inline asm
- From: "gcc.hall at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Thu, 23 Jun 2016 11:07:42 +0000
- Subject: [Bug target/63359] aarch64: 32bit registers in inline asm
- Auto-submitted: auto-generated
- References: <bug-63359-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359
--- Comment #11 from Jeremy <gcc.hall at gmail dot com> ---
int32_t n;
asm( "str %1,[%0],#4" : "+r" (ptr) : "r" (n) : "memory" );
Caught me until I just happened to examine the assembler.
Of course %w1 works - but then I need SEPARATE code for 32-bit ARM and for
aarch64.
Now arnv8 has two register sizes, I ask also, please could it work like x86 and
use the operand size to determine which to emit, x or w.