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[Bug target/70355] [5/6 Regression] ICE: in simplify_subreg_concatn, at lower-subreg.c:617 with -funroll-loops -mavx512f
- From: "rth at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Tue, 29 Mar 2016 00:14:14 +0000
- Subject: [Bug target/70355] [5/6 Regression] ICE: in simplify_subreg_concatn, at lower-subreg.c:617 with -funroll-loops -mavx512f
- Auto-submitted: auto-generated
- References: <bug-70355-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70355
--- Comment #2 from Richard Henderson <rth at gcc dot gnu.org> ---
Created attachment 38113
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=38113&action=edit
proposed patch
Testing the following, which works on the reduced test case.
As a missed-optimization, we really ought to be handling logic operations on
these wide types via normal sse logic insns. Perhaps not for V1TI, but
definitely for V2TI and V4TI. There's no point in breaking them down into
4 and 8 DImode operations, respectively.