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[Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0
- From: "law at redhat dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Wed, 23 Mar 2016 17:21:23 +0000
- Subject: [Bug rtl-optimization/70164] [6 Regression] Code/performance regression due to poor register allocation on Cortex-M0
- Auto-submitted: auto-generated
- References: <bug-70164-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70164
--- Comment #12 from Jeffrey A. Law <law at redhat dot com> ---
Slight correction. I was looking at the wrong part of the dump when I said
cse1 didn't change insn 28. It is cse1 that changes insn 28. So this is
strictly an issue with the transformations cse1 makes.