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[Bug target/67260] [sh] Register spill bug for sibcall+complex+softfloat
- From: "amonakov at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Sat, 06 Feb 2016 16:42:04 +0000
- Subject: [Bug target/67260] [sh] Register spill bug for sibcall+complex+softfloat
- Auto-submitted: auto-generated
- References: <bug-67260-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67260
--- Comment #2 from Alexander Monakov <amonakov at gcc dot gnu.org> ---
(added SH maintainers, Oleg Endo and Kaz Kojima to Cc)
In response to the last sentence in my analysis, on IRC Rich pointed out that
using r1/r2/r3 should be better that r0 because some instruction can operate
only on r0 so that would constrain scheduling.