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[Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- From: "ktkachov at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Tue, 27 Oct 2015 18:33:10 +0000
- Subject: [Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64
- Auto-submitted: auto-generated
- References: <bug-68102-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102
--- Comment #3 from ktkachov at gcc dot gnu.org ---
Author: ktkachov
Date: Tue Oct 27 18:32:37 2015
New Revision: 229455
URL: https://gcc.gnu.org/viewcvs?rev=229455&root=gcc&view=rev
Log:
[AArch64] PR 68102: Check that operand is REG before checking the REGNO in
mov-immediate splitters
PR target/68102
* config/aarch64/aarch64.md (*movsi_aarch64): Check that
operands[0] is a reg before taking its REGNO in split condition.
(*movdi_aarch64): Likewise.
* gcc.target/aarch64/pr68102_1.c: New test.
Added:
trunk/gcc/testsuite/gcc.target/aarch64/pr68102_1.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/aarch64/aarch64.md
trunk/gcc/testsuite/ChangeLog