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[Bug target/67366] Poor assembly generation for unaligned memory accesses on ARM v6 & v7 cpus
- From: "rguenther at suse dot de" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Thu, 27 Aug 2015 14:36:28 +0000
- Subject: [Bug target/67366] Poor assembly generation for unaligned memory accesses on ARM v6 & v7 cpus
- Auto-submitted: auto-generated
- References: <bug-67366-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67366
--- Comment #10 from rguenther at suse dot de <rguenther at suse dot de> ---
On Thu, 27 Aug 2015, rearnsha at gcc dot gnu.org wrote:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67366
>
> --- Comment #9 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
> Does that really do the right thing? That is, does force_reg understand a
> misaligned memory op?
>
> Also, what if one memory operand is aligned, but the other not? Don't we want
> to have the right combination of aligned/misaligned instructions?
I think you never get two MEMs, you at most get a constant on the
RHS of a store.