[Bug target/67071] New: GCC misses an optimization to load vector constants

["meissner at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67071

            Bug ID: 67071
           Summary: GCC misses an optimization to load vector constants
           Product: gcc
           Version: 6.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: meissner at gcc dot gnu.org
  Target Milestone: ---
              Host: powerpc64-unknown-linux-gnu
            Target: powerpc64-unknown-linux-gnu
             Build: powerpc64-unknown-linux-gnu

Gcc has a logic error in rs6000.h which prevents it from being able to load
vector constants with the most significant bit set.

The code is:
#define EASY_VECTOR_MSB(n,mode)                                         \
  (((unsigned HOST_WIDE_INT)n) ==                                       \
   ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))

However, if you look at the const_vector that is passed to
easy_altivec_constant, the constant is sign extended, and EASY_VECTOR_MSB would
not match.

If we instead define EASY_VECTOR_MSG to do the mask before doing the comparison
the test will succeed, and the code will generate the vector splat integer
operation followed by vector shift left.

#define EASY_VECTOR_MSB(n,mode)                                         \
  ((((unsigned HOST_WIDE_INT)n) & GET_MODE_MASK (mode)) ==              \
   ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))

A further optimization would be to recognize vector constants where the upper
part can be formed via vector splat integer and then the bottom bits are all 0
or all 1, and we can use VSLDOI instruction with a secondary register that is
all 0's or all 1's.