[Bug middle-end/66588] New: combine should try transforming if_then_else of zero_extends into zero_extend of if_then_else

["ktkachov at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66588

            Bug ID: 66588
           Summary: combine should try transforming if_then_else of
                    zero_extends into zero_extend of if_then_else
           Product: gcc
           Version: 6.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ktkachov at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64*

Consider the code:

unsigned long
foo (unsigned int a, unsigned int b, unsigned int c)
{
  return a ? b : c;
}

On aarch64 this generates:
foo:
        uxtw    x1, w1
        cmp     w0, wzr
        uxtw    x2, w2
        csel    x0, x2, x1, eq
        ret

where in fact it could generate:
        cmp      w0, #0
        csel    w0, w1, w2, ne
        ret

A write to the 32-bit w-register implicitly zero-extends the value up to the
full
64 bits of an x-register.

This is reflected in aarch64.md by the cmovsi_insn_uxtw pattern that matches:
(set (dest:DI)
     (zero_extend:DI
        (if_then_else:SI (cond) (src1:SI) (src2:SI))
     )
)

However, this doesn't get matched because combine instead tries to match
(set (dest:DI)
     (if_then_else:DI (cond)
                      (zero_extend:DI (src1:SI))
                      (zero_extend:DI (src2:SI))
     )
)

If I change the pattern to the second form then I get the desired codegen.
However, it seems that combine should really be trying that transformation by
itself.