[Bug rtl-optimization/66556] Wrong code-generation for armv7-a big-endian at -Os

["renlin at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66556

--- Comment #1 from renlin at gcc dot gnu.org ---
(insn 22 94 24 4 (set (reg:SI 140 [ g+2 ])
        (zero_extend:SI (mem/c:HI (post_modify:SI (reg/f:SI 156)
                    (plus:SI (reg/f:SI 156)
                        (const_int 20 [0x14]))) [5 g+4 S2 A32]))) test.c:36 159
{*arm_zero_extendhisi2_v6}
     (expr_list:REG_INC (reg/f:SI 156)
        (expr_list:REG_EQUAL (zero_extend:SI (mem/c:HI (const:SI (plus:SI
(symbol_ref:SI ("*.LANCHOR0") [flags 0x182])
                            (const_int 256 [0x100]))) [5 g+4 S2 A32]))
            (nil))))
(insn 24 22 25 4 (set (subreg:SI (reg:HI 141 [ D.4259 ]) 0)
        (zero_extract:SI (reg:SI 140 [ g+2 ])
            (const_int 15 [0xf])
            (const_int 1 [0x1]))) test.c:36 138 {extzv_t2}
     (expr_list:REG_DEAD (reg:SI 140 [ g+2 ])
        (nil)))
(insn 25 24 27 4 (set (reg:SI 142 [ D.4255 ])
        (zero_extend:SI (reg:HI 141 [ D.4259 ]))) test.c:36 159
{*arm_zero_extendhisi2_v6}
     (expr_list:REG_DEAD (reg:HI 141 [ D.4259 ])
        (nil)))
(insn 33 32 34 4 (set (reg:CC 100 cc)
        (compare:CC (reg:SI 142 [ D.4255 ])
            (reg:SI 150 [ D.4255 ]))) test.c:36 188 {*arm_cmpsi_insn}
     (expr_list:REG_DEAD (reg:SI 150 [ D.4255 ])
        (expr_list:REG_DEAD (reg:SI 142 [ D.4255 ])
            (nil))))
(insn 34 33 36 4 (set (reg:SI 152)
        (ltu:SI (reg:CC 100 cc)
            (const_int 0 [0]))) test.c:36 198 {*mov_scc}
     (expr_list:REG_DEAD (reg:CC 100 cc)
        (nil)))

In combine pass, the above rtx are simplified combined and insn 22, 24, 25, 33
are marked as deleted. However, the side-effect of insn 22, post_modify, is not
preserved.

(insn 43 41 45 4 (set (mem/c:HI (plus:SI (reg/f:SI 156)
                (const_int 8 [0x8])) [4 MEM[(short int *)&i + 8B]+0 S2 A16])
So for insn 43, the data is stored in the wrong place.