This is the mail archive of the
gcc-bugs@gcc.gnu.org
mailing list for the GCC project.
[Bug target/53513] [SH] Add support for fschg and fpchg insns and improve fenv support
- From: "olegendo at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Wed, 15 Oct 2014 22:07:57 +0000
- Subject: [Bug target/53513] [SH] Add support for fschg and fpchg insns and improve fenv support
- Auto-submitted: auto-generated
- References: <bug-53513-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53513
--- Comment #29 from Oleg Endo <olegendo at gcc dot gnu.org> ---
(In reply to Oleg Endo from comment #28)
> Created attachment 33727 [details]
> Using virtual FPSCR registers to model insn dependencies
>
> The problem is the define_split and the peephole2 patterns below the
> "fpu_switch" insn. I don't know how/if that was working before. I've
> removed the peephole2 pattern and rewrote the split pattern, which fixes the
> failure above. I'll re-test the whole thing again.
With this patch there are no new failures for -m4 -ml and -m4 -mb here, except
the ISR failures. I'll also test it for the other combinations later. I'd
like to get the current sh4 working version first. Then fix other niche
problems with ISRs or SH2E. Kaz, what do you think?