[Bug middle-end/58330] New: powerpc64 atomic store split in two

["anton at samba dot org" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58330

            Bug ID: 58330
           Summary: powerpc64 atomic store split in two
           Product: gcc
           Version: 4.8.2
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: anton at samba dot org

We found an issue when building the powerpc64 little endian kernel where a 64
bit store was split into two 32 bit stores. Since there is no 64 bit byte
reversed store on POWER6 and earlier, gcc decided to use two 32 bit byte
reversed stores. We were unable to fix this, even with atomic builtins.

I think splitting the store even in the non atomic builtin case is suspect
since we have lots of places in the kernel that rely on naturally aligned loads
and stores being done atomically.

An example:

static inline void __raw_writeq (unsigned long v, void *addr)
{
#if 1
        __atomic_store_n ((unsigned long *) addr, v, __ATOMIC_RELAXED);
#else
        *(volatile unsigned long *)addr = v;
#endif
}

void foo (void *addr, unsigned long start)
{
        unsigned long reverse = __builtin_bswap64 (start);
        __raw_writeq (reverse, addr);
}

gives:

    li 9,4
    srdi 10,4,32
    stwbrx 4,0,3
    stwbrx 10,9,3