[Bug target/51244] [SH] Inefficient conditional branch and code around T bit

["olegendo at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51244

--- Comment #62 from Oleg Endo <olegendo at gcc dot gnu.org> ---
(In reply to Laurent Aflonsi from comment #61)
> 
> More generally, I'm surprised to see that optimization at mapping level,
> isn't this a generic problematic that should be handled at rtl dead code
> elimination stage on the T bit register ?

Actually, it is a kind of generic case.  Dead code elimination would not do
these kind of logic folding.  Usually this kind of stuff handled by the combine
pass which can figure out some redundant operations or operations that cancel
each other out.  However, combine's logic is also limited and it the overall T
bit handling is a bit shaky.  That's why I introduced the additional
elimination handling that is done in the split pass after the combine pass on
insns that combine didn't catch.  I didn't want to introduce another rtl pass
just for this and touching the combine pass also didn't seem attractive since
all the other backends depend on its behavior.

Maybe it would be better to switch T_REG from SImode to BImode, which reflects
reality.  This should be relatively straight forward to do.

Another idea would be to try out using CCmode.  There some additional
optimizations done on CCmode.  However, this is a bigger change.