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[Bug target/54239] Not able to generate "prefetch" (prefetch read) instruction using -m3dnow or -mprfchw
- From: "venkataramanan.kumar at amd dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Mon, 13 Aug 2012 14:33:14 +0000
- Subject: [Bug target/54239] Not able to generate "prefetch" (prefetch read) instruction using -m3dnow or -mprfchw
- Auto-submitted: auto-generated
- References: <bug-54239-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54239
--- Comment #5 from Venkataramanan <venkataramanan.kumar at amd dot com> 2012-08-13 14:33:14 UTC ---
(In reply to comment #4)
> BTW, why do you care about the prefetch insn? Isn't it obsoleted by the SSE
> ISA prefetches anyway (unlike prefetchw)?
Hi Jakub, as for as fam15H processors what I know is they are exactly same.
Yes I can use -mprfchw and generate prefecthw instruction and use prefetchts
instead of prefetch instruction.
But there is a mention in SWOG guide of amdfam15 that their functionalities
could change in future.
(Snip)
AMD Family 15h processors implement the PREFETCHT0, PREFETCHT1, and PREFETCHT2
instructions in exactly the same way as the PREFETCH instruction. That is, the
data is brought into the L1 data cache. This functionality could change in
future implementations of the AMD Family 15h
processor
(Snip)