[Bug rtl-optimization/50088] movzbl is generated instead of movl

["enkovich.gnu at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50088

--- Comment #2 from Ilya Enkovich <enkovich.gnu at gmail dot com> 2011-08-15 13:24:05 UTC ---
Actually we do not need any zero extensions here. Zero extended load appears
only after IRA if we have to spill/fill register.

Here is c code from reproducer:

      n1 = (n1 + 1) & 15;
      s += arr[i] << n1;

RTL before IRA:

(insn 67 66 68 4 (parallel [
            (set (reg/v:SI 97 [ n1 ])
                (plus:SI (reg/v:SI 97 [ n1 ])
                    (const_int 1 [0x1])))
            (clobber (reg:CC 17 flags))
        ]) test_movzbl.c:18 249 {*addsi_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))

(insn 68 67 70 4 (parallel [
            (set (reg/v:SI 97 [ n1 ])
                (and:SI (reg/v:SI 97 [ n1 ])
                    (const_int 15 [0xf])))
            (clobber (reg:CC 17 flags))
        ]) test_movzbl.c:18 385 {*andsi_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))

(insn 70 68 71 4 (set (reg:SI 262)
        (mem:SI (reg:SI 224 [ ivtmp.52 ]) [2 MEM[base: D.2889_232, offset:
0B]+0 S4 A32])) test_movzbl.c:20 64 {*movsi_internal}
     (nil))

(insn 71 70 72 4 (parallel [
            (set (reg:SI 262)
                (ashift:SI (reg:SI 262)
                    (subreg:QI (reg/v:SI 97 [ n1 ]) 0)))
            (clobber (reg:CC 17 flags))
        ]) test_movzbl.c:20 502 {*ashlsi3_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (expr_list:REG_EQUAL (ashift:SI (mem:SI (reg:SI 224 [ ivtmp.52 ]) [2
MEM[base: D.2889_232, offset: 0B]+0 S4 A32])
                (subreg:QI (reg/v:SI 97 [ n1 ]) 0))
            (nil))))

IRA then introduces fill for shift instruction and use byte load for it:

(insn 155 70 71 4 (set (reg:QI 2 cx)
        (mem/c:QI (reg/f:SI 7 sp) [4 %sfp+-28 S1 A32])) test_movzbl.c:20 66
{*movqi_internal}
     (nil))

(insn 71 155 72 4 (parallel [
            (set (reg:SI 5 di [262])
                (ashift:SI (reg:SI 5 di [262])
                    (reg:QI 2 cx)))
            (clobber (reg:CC 17 flags))
        ]) test_movzbl.c:20 502 {*ashlsi3_1}
     (expr_list:REG_EQUAL (ashift:SI (mem:SI (reg:SI 0 ax [orig:224 ivtmp.52 ]
[224]) [2 MEM[base: D.2889_232, offset: 0B]+0 S4 A32])
            (subreg:QI (mem/c:SI (reg/f:SI 7 sp) [4 %sfp+-28 S4 A32]) 0))
        (nil)))

Load for shift then is emitted as movzbl.