[Bug tree-optimization/48616] -ftree-vectorize -mxop miscompiles right shift

["jakub at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48616

--- Comment #6 from Jakub Jelinek <jakub at gcc dot gnu.org> 2011-04-15 13:39:08 UTC ---
I should mention it is the only vpsrad insn in the testcase.

In *.cunroll we have:

  [pr48616.C : 113:76] D.52396_86 = MEM[(const AliasingEntryType *
{ref-all})&shifts];
...
  [pr48616.C : 113:76] D.52395_89 = MEM[(const AliasingEntryType *
{ref-all})&shifts + 4B];
...
  [pr48616.C : 113:76] D.52394_92 = MEM[(const AliasingEntryType *
{ref-all})&shifts + 8B];
...
  [pr48616.C : 113:76] D.52393_95 = MEM[(const AliasingEntryType *
{ref-all})&shifts + 12B];
...

<L12>:
  [pr48616.C : 1721:5] [pr48616.C : 1721] [pr48616.C : 1721] MEM[(struct Vector
*)&a].data = { 68719476752, 68719476752 };
  [pr48616.C : 1288:172] D.52507_129 = MEM[(AliasingEntryType & {ref-all})&a];
  [pr48616.C : 1288:172] D.52506_131 = D.52507_129 >> D.52396_86;
  [pr48616.C : 1288:172] MEM[(AliasingEntryType & {ref-all})&a] = D.52506_131;
  [pr48616.C : 1288:258] D.52504_132 = MEM[(AliasingEntryType & {ref-all})&a +
4];
  [pr48616.C : 1288:258] D.52503_134 = D.52504_132 >> D.52395_89;
  [pr48616.C : 1288:258] MEM[(AliasingEntryType & {ref-all})&a + 4] =
D.52503_134;
  [pr48616.C : 1288:344] D.52501_135 = MEM[(AliasingEntryType & {ref-all})&a +
8];
  [pr48616.C : 1288:344] D.52500_137 = D.52501_135 >> D.52394_92;
  [pr48616.C : 1288:344] MEM[(AliasingEntryType & {ref-all})&a + 8] =
D.52500_137;
  [pr48616.C : 1288:430] D.52498_138 = MEM[(AliasingEntryType & {ref-all})&a +
12];
  [pr48616.C : 1288:430] D.52497_140 = D.52498_138 >> D.52393_95;
  [pr48616.C : 1288:430] MEM[(AliasingEntryType & {ref-all})&a + 12] =
D.52497_140;

*.slp has:
<L12>:
  [pr48616.C : 1721:5] # .MEMD.52319_50 = VDEF <.MEMD.52319_1126>
  [pr48616.C : 1721] [pr48616.C : 1721] MEM[(struct VectorD.34523
*)&aD.38703].dataD.34590 = { 68719476752, 68719476752 };
  # PT = anything 
  # ALIGN = 16, MISALIGN = 0
  vect_p.1912D.63297_1085 = &MEM[(AliasingEntryTypeD.34571 &
{ref-all})&aD.38703];
  [pr48616.C : 1288:172] # VUSE <.MEMD.52319_50>
  vect_var_.1913D.63298_534 = MEM[(AliasingEntryTypeD.34571 &
{ref-all})vect_p.1912D.63297_1085];
  [pr48616.C : 1288:172] # VUSE <.MEMD.52319_50>
  D.52507_129 = MEM[(AliasingEntryTypeD.34571 & {ref-all})&aD.38703];
  [pr48616.C : 1288:172] vect_var_.1914D.63299_575 = vect_var_.1913D.63298_534
>> D.52396_86;
  [pr48616.C : 1288:172] D.52506_131 = D.52507_129 >> D.52396_86;
  # PT = anything 
  # ALIGN = 16, MISALIGN = 0
  vect_p.1918D.63303_576 = &MEM[(AliasingEntryTypeD.34571 &
{ref-all})&aD.38703];
  [pr48616.C : 1288:258] # VUSE <.MEMD.52319_50>
  D.52504_132 = MEM[(AliasingEntryTypeD.34571 & {ref-all})&aD.38703 + 4];
  [pr48616.C : 1288:258] D.52503_134 = D.52504_132 >> D.52395_89;
  [pr48616.C : 1288:344] # VUSE <.MEMD.52319_50>
  D.52501_135 = MEM[(AliasingEntryTypeD.34571 & {ref-all})&aD.38703 + 8];
  [pr48616.C : 1288:344] D.52500_137 = D.52501_135 >> D.52394_92;
  [pr48616.C : 1288:430] # VUSE <.MEMD.52319_50>
  D.52498_138 = MEM[(AliasingEntryTypeD.34571 & {ref-all})&aD.38703 + 12];
  [pr48616.C : 1288:430] D.52497_140 = D.52498_138 >> D.52393_95; 
  [pr48616.C : 1288:430] # .MEMD.52319_580 = VDEF <.MEMD.52319_50>
  MEM[(AliasingEntryTypeD.34571 & {ref-all})vect_p.1918D.63303_576] =
vect_var_.1914D.63299_575;