[Bug rtl-optimization/47862] New: Incorrect code for spilling a vector register

["pthaugen at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47862

           Summary: Incorrect code for spilling a vector register
           Product: gcc
           Version: 4.6.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: pthaugen@gcc.gnu.org
                CC: bergner@gcc.gnu.org, meissner@gcc.gnu.org
              Host: powerpc64-linux
            Target: powerpc64-linux
             Build: powerpc64-linux


Created attachment 23444
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=23444
testcase

Tracked down an issue in cpu2006 benchmark 456.hmmer where incorrect code is
generated when spilling a vector register. The normal floating point stfd/lfd
insns are being generated, which only spills half the vector (allowing the
other half to get clobbered across a function call).

Attatched testcase was compiled with: gcc -S -m64 -O3 -mcpu=power7
-mveclibabi=mass -ffast-math spill.c

Spill is occuring in the vectorized loop with expd2() calls. A snippet of that
loop showing the use vr11 as vector and incorrect spill follows. There are a
few other regs spilled in similar fashion in the loop.


        xvmuldp 11,58,12
        xvmuldp 34,57,12
        xvadddp 10,63,60
        stfd 11,144(1)
        xvadddp 53,53,10
        bl expd2
        nop
        lfd 11,144(1)
        xxlor 62,34,34
        xxlor 34,11,11
        xvmuldp 57,57,62
        bl expd2