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[Bug target/45913] [4.6 Regression] ICE: in insn_default_length, at config/i386/i386.md:584 with -fselective-scheduling2 -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops
- From: "hjl.tools at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Thu, 7 Oct 2010 01:31:24 +0000
- Subject: [Bug target/45913] [4.6 Regression] ICE: in insn_default_length, at config/i386/i386.md:584 with -fselective-scheduling2 -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops
- Auto-submitted: auto-generated
- References: <bug-45913-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45913
H.J. Lu <hjl.tools at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |ubizjak at gmail dot com
--- Comment #3 from H.J. Lu <hjl.tools at gmail dot com> 2010-10-07 01:31:21 UTC ---
Can we implement it
(insn:TI 110 50 107 (parallel [
(set (reg/v:SI 3 bx [orig:82 j ] [82])
(and:SI (mem/c:SI (plus:DI (reg/f:DI 7 sp)
(const_int 4 [0x4])) [3 %sfp+-524 S4 A32])
(const_int 255 [0xff])))
(clobber (reg:CC 17 flags))
]) -1
(nil))
as "movzbl m8,reg"?