[Bug rtl-optimization/30688] Branch registers loaded too late on ia64

["steven at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>]

------- Comment #5 from steven at gcc dot gnu dot org  2009-03-16 08:46 -------
Can someone point me to the IA64 optimiation manuals mentioned in comment #0?  

I'm looking for some answers, for example:

* Which branch registers can I use? bt-load can actually perform register
renaming.  It has to, of course, because bt-load runs after the register
allocator. The register allocator prefers to always use tr0 on sh64, and it
probably always tries to use the same branch register on ia64 too.  So register
renaming is a Good Thing here.  But which regs can I use on IA64?

* What does "as early as possible" mean in comment #0?  Are there
recommendations for what is considered "too early" (for example due to
interactions with calls and such)?

* What happens if a value is assigned to a branch register on IA64?  Is the
prefetcher always triggered?  What is the latency of the prefetching after a
branch register has been assigned a value?

* Is there a possibility to add a prediction hint to say "branch register A is
more likely to be used than branch register B" when multiple branch registers
are assigned a value in the same basic block?


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=30688