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[Bug rtl-optimization/17104] Non-optimal code generation for bitfield initialization
- From: "mmitchel at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 20 Sep 2004 01:56:07 -0000
- Subject: [Bug rtl-optimization/17104] Non-optimal code generation for bitfield initialization
- References: <20040819145911.17104.steinmtz@us.ibm.com>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Additional Comments From mmitchel at gcc dot gnu dot org 2004-09-20 01:56 -------
In 32-bit mode the initial RTL looks like:
(set:SI (reg:SI 124) (mem:SI (reg:SI 122)))
...
(set:SI (mem:SI (reg:SI 122)) (reg:SI 125))
CSE recognizes that at this point the MEM and REG 125 contain the same value,
and therefore replaces the next read of the MEM with REG 125.
In 64-bit mode, the RTL looks like:
(set:DI (reg:DI 125) (zero_extend:DI (mem:SI (reg:DI 123))))
...
(set:SI (mem:SI (reg:SI 123)) (reg:SI 127))
The zero-extends applied to the load prevent CSE from recognizing that the MEM
written and the MEM read are the same.
There are several possible approaches to consider:
(a) Modify the PowerPC machine description to emit an SImode load,
instead of the zero-extend sequence. (The hardware instruction
actually *is* zero-extending, which is presumably why the
machine description generates the zero-extension.)
(b) Modify the PowerPC machine description to emit the
zero-extension as a separate instruction. (And hope that the
compiler will combine them into one instruction later if
possible.)
(c) Modify CSE to recognize the zero_extend idiom and replace the
operand to the zero_extend.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17104