[Bug optimization/13951] [tree-ssa] cselib ICE during x86-64 kernel compile with treessa

["jh at suse dot cz" <gcc-bugzilla at gcc dot gnu dot org>]

------- Additional Comments From jh at suse dot cz  2004-02-05 10:18 -------
Subject: Re:  [tree-ssa] cselib ICE during  x86-64 kernel compile with treessa

> 
> ------- Additional Comments From rth at redhat dot com  2004-02-05 09:47 -------
> Subject: Re:  [tree-ssa] cselib ICE during  x86-64 kernel compile with treessa
> 
> On Thu, Feb 05, 2004 at 09:35:31AM +0100, Jan Hubicka wrote:
> > To deal with this correctly, we would have to teach cselib to track down
> > such a multi sets and invalidate result of the register immediately
> > after processing.
> 
> No we don't.  We can treat this just as CLOBBER.

I don't quite follow it.  I see that in this case the asm statement is
doing ugly way of clobber, so first question is whether we want to allow
asm statements as a special case, or we want to allow generic
instructions to have mutiple sets with the same destination?

You mean that while processing the second set, I shall notice that it
already has recorded equivalence with the first set, invalidate it and
record equivalence with somple placeholder RTX?
(the problem is that if I only invalidate it, the third set to same
destination won't notice it and record new equivalence, that is
precisely what is unsafe to do)

I am still concerned about the fact that many other places looks for
sets and blindly trust that if register is an destination of the set, it
will contain the value, so I don't really like such instructions lurking
around especially when they are easy to avoid.

Honza
> 
> 
> r~
> 
> 
> -- 
> 
> 
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=13951
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=13951