Re: High priority target/6981 is fixed on CVS mainline

[Jakub Jelinek <jakub at redhat dot com>]

On Tue, Oct 15, 2002 at 08:55:33AM -0600, Roger Sayle wrote:
> 
> Hi Jakub,
> 
> I notice that GNATS PR target/6981 is currently assigned to you.
> You'll be pleased to hear the good news that this has now been
> fixed on CVS mainline.  Unfortunately, the problem is still present
> on the 3.2 branch, and it isn't clear which patch actually fixed
> the problem.

If any. Reload problems might go away with register allocator changes
or other directly unrelated changes.

This particular bug is about reloading of:
(insn 39 37 44 (parallel[
            (set (mem/f:DI (symbol_ref:SI ("m")) [4 m+0 S8 A64])
                (plus:DI (mem:DI (plus:SI (mult:SI (reg:SI 64)
                                (const_int 8 [0x8]))
                            (reg/v/f:SI 59)) [4 S8 A64])
                    (mem:DI (plus:SI (mult:SI (reg/v:SI 61)
                                (const_int 8 [0x8]))
                            (reg/v/f:SI 59)) [4 S8 A64])))
            (clobber (reg:CC 17 flags))
        ] ) 185 {*adddi3_1} (insn_list 22 (insn_list 17 (nil)))
    (expr_list:REG_DEAD (reg:SI 64)
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (expr_list:REG_DEAD (reg/v:SI 61)
                (nil)))))

Reloads for insn # 39
Reload 0: reload_in (SI) = (reg:SI 64)
        INDEX_REGS, RELOAD_OTHER (opnum = 0)
        reload_in_reg: (reg:SI 64)
        reload_reg_rtx: (reg:SI 0 eax)
Reload 1: reload_in (SI) = (reg/v/f:SI 59)
        GENERAL_REGS, RELOAD_OTHER (opnum = 0)
        reload_in_reg: (reg/v/f:SI 59)
        reload_reg_rtx: (reg:SI 1 edx)
Reload 2: reload_in (SI) = (reg/v:SI 61)
        INDEX_REGS, RELOAD_OTHER (opnum = 2)
        reload_in_reg: (reg/v:SI 61)
        reload_reg_rtx: (reg:SI 0 eax)
Reload 3: GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 2)
        reload_in_reg: (reg/v/f:SI 59)
        reload_reg_rtx: (reg:SI 1 edx)
Reload 4: reload_in (DI) = (mem:DI (plus:SI (mult:SI (reg:SI 64)
                                                            (const_int 8 [0x8]))
                                                        (reg/v/f:SI 59)) [4 S8 A64])
        reload_out (DI) = (mem/f:DI (symbol_ref:SI ("m")) [4 m+0 S8 A64])
        GENERAL_REGS, RELOAD_OTHER (opnum = 0)
        reload_in_reg: (mem:DI (plus:SI (mult:SI (reg:SI 64)
                                                            (const_int 8 [0x8]))
                                                        (reg/v/f:SI 59)) [4 S8 A64])
        reload_out_reg: (mem/f:DI (symbol_ref:SI ("m")) [4 m+0 S8 A64])
        reload_reg_rtx: (reg:DI 4 rsi)
Reload 5: reload_in (DI) = (mem:DI (plus:SI (mult:SI (reg/v:SI 61)
                                                            (const_int 8 [0x8]))
                                                        (reg/v/f:SI 59)) [4 S8 A64])
        GENERAL_REGS, RELOAD_OTHER (opnum = 2), optional
        reload_in_reg: (mem:DI (plus:SI (mult:SI (reg/v:SI 61)
                                                            (const_int 8 [0x8]))
                                                        (reg/v/f:SI 59)) [4 S8 A64])

which creates bogus:

(insn 104 37 107 (set (reg:SI 0 eax)
        (mem:SI (plus:SI (reg/f:SI 6 ebp)
                (const_int -24 [0xffffffe8])) [7 S4 A8])) 45 {*movsi_1} (nil)
    (nil))

(insn 107 104 110 (set (reg:SI 1 edx)
        (mem/f:SI (plus:SI (reg/f:SI 6 ebp)
                (const_int 12 [0xc])) [3 r+0 S4 A32])) 45 {*movsi_1} (nil)
    (nil))

(insn 110 107 113 (set (reg:SI 0 eax)
        (mem:SI (plus:SI (reg/f:SI 6 ebp)
                (const_int -20 [0xffffffec])) [6 rs2 S4 A8])) 45 {*movsi_1} (nil)
    (nil))

(insn 113 110 39 (set (reg:DI 4 rsi)
        (mem:DI (plus:SI (mult:SI (reg:SI 0 eax)
                    (const_int 8 [0x8]))
                (reg:SI 1 edx)) [4 S8 A64])) 83 {*movdi_2} (nil)
    (nil))

(insn 39 113 116 (parallel[
            (set (reg:DI 4 rsi)
                (plus:DI (reg:DI 4 rsi)
                    (mem:DI (plus:SI (mult:SI (reg:SI 0 eax)
                                (const_int 8 [0x8]))
                            (reg:SI 1 edx)) [4 S8 A64])))
            (clobber (reg:CC 17 flags))
        ] ) 185 {*adddi3_1} (insn_list 22 (insn_list 17 (nil)))
    (nil))

(insn 116 39 44 (set (mem/f:DI (symbol_ref:SI ("m")) [4 m+0 S8 A64])
        (reg:DI 4 rsi)) 83 {*movdi_2} (nil)
    (nil))

(note that reload chose to reload both pseudo 61 and 64 into the same
hard register %eax. If gcc were to put insn 104 right before insn 39
and not the other way around, it would work just fine; $ebp-24 is pseudo 64
home, $ebp-20 is pseudo 61 home, $ebp+12 is pseudo 59 home).

> I was wondering if you had already identified the patch or patches
> that need to be backported, or whether you'd like me to start binary
> searching in CVS?

If you have time. Note that I think it passed on mainline already when I
looked at it back in July, though am not 100% sure.

	Jakub