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Re: target/6142: sil, dil, spl, bpl are being used in ia32 compiles
- From: kelley dot r dot cook at gm dot com
- To: gcc-bugs at gcc dot gnu dot org, gcc-prs at gcc dot gnu dot org, gcc-patches at gcc dot gnu dot org
- Cc: jakub at gcc dot gnu dot org, kelleycook at comcast dot net, rth at redhat dot com
- Date: Fri, 12 Apr 2002 17:45:37 -0400
- Subject: Re: target/6142: sil, dil, spl, bpl are being used in ia32 compiles
>Synopsis: sil, dil, spl, bpl are being used in ia32 compiles
>
>State-Changed-From-To: analyzed->closed
>State-Changed-By: jakub
>State-Changed-When: Wed Apr 3 10:41:24 2002
>State-Changed-Why:
> See http://gcc.gnu.org/ml/gcc-patches/2002-04/msg00126.html
>You need to use "q" constraints, not "r".
>
>http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=6142
After thinking some more about this, this behavior just does not seem kosher ...
even for illegal code. IMHO, there is no instance where a compiler should
generate references to registers which do not exist for a particular
architecture.
Therefore I am submitting my original idea for fixing the problem. It didn't
entirely work but instead leads to an ICE for this particular testcase. At the
very least getting an ICE with a line number might have made locating the coding
bugs easier for me than having the assembler crash with non-existant register
names.
If this patch is accepted then I suggest reopening this PR as an
ice-on-illegal-code.
Bootstrapped and checked on i686-pc-cygwin
FWIW, I intially was getting an additional assembler ICE in
gcc.c-torture/execute/920501-1.c at '-O3 -fomit-frame-pointer', which went away
after I removed the obvious extra commas.
Kelley Cook [no write privledges]
2002-04-12 Kelley Cook <kelleycook@comcast.net>
PR target/6142
* config/i386/i386.h (QI_REGISTER_NAMES): Only four registers for
ia32. Remove extra comma.
(QI_HIGH_REGISTER_NAMES): Remove extra comma.
--- i386.h.orig Fri Mar 29 18:21:38 2002
+++ i386.h Fri Apr 12 14:22:46 2002
@@ -2798,14 +2798,19 @@
number as al, and ax.
*/
+#if TARGET_64BIT
#define QI_REGISTER_NAMES \
-{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
+{ "al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl" }
+#else
+#define QI_REGISTER_NAMES \
+{ "al", "dl", "cl", "bl" }
+#endif
/* These parallel the array above, and can be used to access bits 8:15
of regs 0 through 3. */
#define QI_HIGH_REGISTER_NAMES \
-{"ah", "dh", "ch", "bh", }
+{ "ah", "dh", "ch", "bh" }
/* How to renumber registers for dbx and gdb. */