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MIPS ashldi3_internal bug
- From: Hiroyuki Machida <machida at sm dot sony dot co dot jp>
- To: gcc-bugs at gcc dot gnu dot org, gcc-patches at gcc dot gnu dot org
- Date: Mon, 08 Apr 2002 21:09:44 +0900 (JST)
- Subject: MIPS ashldi3_internal bug
Hi, all
I found that clobber-parameter of "ashldi3_internal",
"ashldi3_internal3", "ashrdi3_internal" and "lshrdi3_internal"
must be early clobbered, in "confg/mips/mips.md". You can see these
bugs in any branches.
Here is a patch, bootstrapped with gcc-3_0-branch.
Please apply this patch to gcc-3_0-branch, gcc-3_1-branch and HEAD.
---
ChangeLog entry:
* gcc/config/mips/mips.md (ashldi3_internal): Add constrain "&" to
clobber-parameter. (ashldi3_internal3):
Likewise. (ashrdi3_internal): Likewise. (lshrdi3_internal): Likewise.
Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.87.4.5
diff -p -U15 -r1.87.4.5 mips.md
--- mips.md 19 Feb 2002 23:16:53 -0000 1.87.4.5
+++ mips.md 8 Apr 2002 10:32:13 -0000
@@ -6466,31 +6466,31 @@ move\\t%0,%z4\\n\\
}
emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
operands[2]));
DONE;
}
operands[3] = gen_reg_rtx (SImode);
}")
(define_insn "ashldi3_internal"
[(set (match_operand:DI 0 "register_operand" "=&d")
(ashift:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
+ (clobber (match_operand:SI 3 "register_operand" "=&d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
"*
{
operands[4] = const0_rtx;
dslots_jump_total += 3;
dslots_jump_filled += 2;
return \"sll\\t%3,%2,26\\n\\
\\tbgez\\t%3,1f\\n\\
\\tsll\\t%M0,%L1,%2\\n\\
\\t%(b\\t3f\\n\\
\\tmove\\t%L0,%z4%)\\n\\
\\n\\
%~1:\\n\\
\\t%(beq\\t%3,%z4,2f\\n\\
@@ -6552,31 +6552,31 @@ move\\t%0,%z4\\n\\
&& !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
&& GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
&& GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
&& (INTVAL (operands[2]) & 32) != 0"
[(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
(set (subreg:SI (match_dup 0) 1) (const_int 0))]
"operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
(define_insn "ashldi3_internal3"
[(set (match_operand:DI 0 "register_operand" "=d")
(ashift:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
+ (clobber (match_operand:SI 3 "register_operand" "=&d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
&& (INTVAL (operands[2]) & 63) < 32
&& (INTVAL (operands[2]) & 63) != 0"
"*
{
int amount = INTVAL (operands[2]);
operands[2] = GEN_INT (amount & 31);
operands[4] = const0_rtx;
operands[5] = GEN_INT ((-amount) & 31);
return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
}"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
@@ -6824,31 +6824,31 @@ move\\t%0,%z4\\n\\
}
emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
operands[2]));
DONE;
}
operands[3] = gen_reg_rtx (SImode);
}")
(define_insn "ashrdi3_internal"
[(set (match_operand:DI 0 "register_operand" "=&d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
+ (clobber (match_operand:SI 3 "register_operand" "=&d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
"*
{
operands[4] = const0_rtx;
dslots_jump_total += 3;
dslots_jump_filled += 2;
return \"sll\\t%3,%2,26\\n\\
\\tbgez\\t%3,1f\\n\\
\\tsra\\t%L0,%M1,%2\\n\\
\\t%(b\\t3f\\n\\
\\tsra\\t%M0,%M1,31%)\\n\\
\\n\\
%~1:\\n\\
\\t%(beq\\t%3,%z4,2f\\n\\
@@ -7205,31 +7205,31 @@ move\\t%0,%z4\\n\\
}
emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
operands[2]));
DONE;
}
operands[3] = gen_reg_rtx (SImode);
}")
(define_insn "lshrdi3_internal"
[(set (match_operand:DI 0 "register_operand" "=&d")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
+ (clobber (match_operand:SI 3 "register_operand" "=&d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
"*
{
operands[4] = const0_rtx;
dslots_jump_total += 3;
dslots_jump_filled += 2;
return \"sll\\t%3,%2,26\\n\\
\\tbgez\\t%3,1f\\n\\
\\tsrl\\t%L0,%M1,%2\\n\\
\\t%(b\\t3f\\n\\
\\tmove\\t%M0,%z4%)\\n\\
\\n\\
%~1:\\n\\
\\t%(beq\\t%3,%z4,2f\\n\\
---
Hiroyuki Machida
Sony Corp.