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Re: Access size problem on ARM architecture
- To: Philip Blundell <philb at gnu dot org>
- Subject: Re: Access size problem on ARM architecture
- From: Richard Earnshaw <rearnsha at arm dot com>
- Date: Mon, 21 May 2001 10:38:44 +0100
- cc: olaf dot wepner at pep dot de, gcc-bugs at gcc dot gnu dot org, Peter Widmann <peter dot widmann at pep dot de>, "Bernhard Nägele" <bernhard dot naegele at pep dot de>, Peter Hedrich <peter dot hedrich at pep dot de>, Richard dot Earnshaw at arm dot com
- Organization: ARM Ltd.
- Reply-To: Richard dot Earnshaw at arm dot com
> >No warnings or errors are displayed.
> >The generated assembly file contains:
> >
> > ldr r3, [r2, #24]! @ loadhi
> >
> >which is wrong since r3 is loaded with a 32 bit value instead of 16 bit.
> >This leads to wrong behaviour of the while statement.
>
> You should find that this instruction is followed by:
>
> mov r3, r3, lsl #16
> cmp r0, e3, lsr #16
>
> or some similar construct that drops the unwanted bits from the register.
> If you are seeing genuinely wrong behaviour, please post a complete testcase
> that exhibits the problem.
>
Phil,
We already have one: PR-2623. I don't have time to look into it at the
moment, but the solution is to split the loadhi_preinc and loadhi_predec
patterns into armv4 and non-armv4 variants, remembering that the offsets
for ldrh are more limited than for ldr.
Similar fixes may also be needed for the post-inc peepholes.
R.