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Access size problem on ARM architecture
- To: gcc-bugs at gcc dot gnu dot org
- Subject: Access size problem on ARM architecture
- From: olaf dot wepner at pep dot de
- Date: Fri, 18 May 2001 13:47:35 +0200
- CC: Peter Widmann <peter dot widmann at pep dot de>,"Bernhard Nägele" <bernhard dot naegele at pep dot de>,Peter Hedrich <peter dot hedrich at pep dot de>
Hello,
I probably found a bug in GCC 2.95.3 compiled for the ARM architecture.
It is possible to demonstrate the error with the following small
program:
void test (void)
{
volatile unsigned short *p = (volatile unsigned short*)
0x12345678;
do
{
p += 12;
} while (*p != 0xabcd);
}
I compile this small prog with the following line:
arm-elf-gcc -Wall -O2 -S testa.c
No warnings or errors are displayed.
The generated assembly file contains:
ldr r3, [r2, #24]! @ loadhi
which is wrong since r3 is loaded with a 32 bit value instead of 16 bit.
This leads to wrong behaviour of the while statement.
The exact version I use is:
Reading specs from /usr/local/lib/gcc-lib/arm-elf/2.95.3/specs
gcc version 2.95.3 20010315 (release)
The parameters given to configure when compiling this compiler where:
--target=arm-elf --with-newlib --enable-languages=c,c++
I tried to fix the bug by modifying gcc/config/arm/arm.md in the
following way:
--- /home/olafwe/amd Fri May 18 13:42:03 2001
+++ arm.md Fri May 18 13:10:47 2001
@@ -5622,7 +5622,7 @@
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& (GET_CODE (operands[2]) != REG
|| REGNO (operands[2]) != FRAME_POINTER_REGNUM)"
- "ldr%?\\t%3, [%0, %2]!\\t%@ loadhi"
+ "ldr%?h\\t%3, [%0, %2]!\\t%@ loadhi"
[(set_attr "type" "load")])
(define_insn "*loadhi_predec"
@@ -5637,7 +5637,7 @@
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& (GET_CODE (operands[2]) != REG
|| REGNO (operands[2]) != FRAME_POINTER_REGNUM)"
- "ldr%?\\t%3, [%0, -%2]!\\t%@ loadhi"
+ "ldr%?h\\t%3, [%0, -%2]!\\t%@ loadhi"
[(set_attr "type" "load")])
(define_insn "*strqi_shiftpreinc"
@@ -5774,7 +5774,7 @@
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
- "ldr%?\\t%5, [%0, %3%S2]!\\t%@ loadhi"
+ "ldr%?h\\t%5, [%0, %3%S2]!\\t%@ loadhi"
[(set_attr "type" "load")])
(define_insn "*loadhi_shiftpredec"
@@ -5791,7 +5791,7 @@
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
- "ldr%?\\t%5, [%0, -%3%S2]!\\t%@ loadhi"
+ "ldr%?h\\t%5, [%0, -%3%S2]!\\t%@ loadhi"
[(set_attr "type" "load")])
; It can also support extended post-inc expressions, but combine
doesn't
@@ -5841,7 +5841,7 @@
&& ! TARGET_SHORT_BY_BYTES
&& REGNO (operands[0]) != REGNO (operands[1])
&& (GET_CODE (operands[2]) != REG || REGNO (operands[0]) != REGNO
(operands[2]))"
- "ldr%?\\t%0, [%1], %2\\t%@ loadhi")
+ "ldr%?h\\t%0, [%1], %2\\t%@ loadhi")
(define_peephole
[(set (match_operand:SI 0 "s_register_operand" "=r")
With this patch applied, the assembly line is correctly created as 16
bit access.
However, I have to less experience in RTL if this change creates
unwanted side
effects and if there are additional errors of the same type.
If you need additional information don't hesitate to ask.
Best regards,
Olaf Wepner.
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