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Re: ARM code generation bug with -O2...
- To: Nick Clifton <nickc at cygnus dot com>
- Subject: Re: ARM code generation bug with -O2...
- From: Richard Earnshaw <rearnsha at arm dot com>
- Date: Mon, 03 Jul 2000 17:57:59 +0100
- Cc: scottb at netwinder dot org, gcc-bugs at gcc dot gnu dot org
- Cc: rearnsha at arm dot com
- Organization: ARM Ltd.
- Reply-To: rearnsha at arm dot com
> Hi Richard,
>
> : This is OK, but incomplete. The tests should be the same as for post-inc
> : ldr. That is, that the base isn't being loaded/stored and that if the
> : increment is a register, it isn't the same register as the base. See the
> : ldr peepholes in the same section for a template.
>
> Ah, good point. OK, here is an extend version of the patch. This
> version adds the check you mentioned above, plus it also adds similar
> checks for the pre-inc peephole that follows after the post-inc
> peepholes.
>
> OK to apply ?
>
> Cheers
> Nick
>
> 2000-07-03 Nick Clifton <nickc@cygnus.com>
>
> * config/arm/arm.md: Fix post increment and pre increment
> peepholes so that they do not generate UNPREDICATBLE opcodes.
> (ie ones where the increment clobbers the source/destination).
OK.
R.