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egcs-1.1 bug - cross compiling
- To: egcs-bugs at cygnus dot com
- Subject: egcs-1.1 bug - cross compiling
- From: DKScully at t-online dot de (Thorsten Kranzkowski)
- Date: Fri, 19 Mar 1999 00:18:41 +0000 (UTC)
Hello!
I encountered a problem with cross-compiling from i386 to alpha. I used
egcs-1.1b (host=i486 target=alpha) to compile glibc-2.1 for the alpha.
I'm sorry I don't remember which source file sowed the error :-(
I also don't remember the exact error-message. It was somthing like "unable to
handle .... movdi ....."
The following conditions apply:
BUILD and HOST system:
i486-pc-linux-gnu
linux kernel 2.2.1
glibc-2.1
binutils 2.9.1.0.16
egcs-2.90.29 980515 (egcs-1.0.3 release) [host=target=i486]
egcs-1.1b [host=i486 target=alpha]
TARGET system:
alpha-noname-linux-gnu
linux kernel 2.2.1
glibc-2.1
(binutils 2.9.1.0.19)
(egcs-1.1b)
I think I found the reason for my problem : it is the second abort() in the
following sample:
------------------- egcs-1.1b/gcc/config/alpha/alpha.md: ---------------------
(define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "")
(match_operand:DI 1 "general_operand" ""))]
""
"
{
rtx tem;
if (GET_CODE (operands[0]) == MEM
&& ! reg_or_0_operand (operands[1], DImode))
operands[1] = force_reg (DImode, operands[1]);
if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
;
else if (GET_CODE (operands[1]) == CONST_INT
&& (tem = alpha_emit_set_const (operands[0], DImode,
(HOST_WIDE_INT) INTVAL (operands[1]), 3)) != 0)
{
if (rtx_equal_p (tem, operands[0]))
DONE;
else
operands[1] = tem;
}
else if (CONSTANT_P (operands[1]))
{
if (TARGET_BUILD_CONSTANTS)
{
#if HOST_BITS_PER_WIDE_INT == 64
HOST_WIDE_INT i;
if (GET_CODE (operands[1]) == CONST_INT)
i = INTVAL (operands[1]);
else if (GET_CODE (operands[1]) == CONST_DOUBLE)
i = CONST_DOUBLE_LOW (operands[1]);
else
abort();
tem = alpha_emit_set_long_const (operands[0], i);
if (rtx_equal_p (tem, operands[0]))
DONE;
else
operands[1] = tem;
#else
abort(); /* <-------------- this one ------ */
#endif
}
else
{
operands[1] = force_const_mem (DImode, operands[1]);
if (reload_in_progress)
{
emit_move_insn (operands[0], XEXP (operands[1], 0));
operands[1] = copy_rtx (operands[1]);
XEXP (operands[1], 0) = operands[0];
}
else
operands[1] = validize_mem (operands[1]);
}
}
else
abort ();
}")
------------------------------------------------------------------------------
Since I realized that the error won't happen if HOST_BITS_PER_WIDE_INT were 64
and gcc has a 64-bit 'long long' type I made the following modification:
------------------------------------------------------------------------------
diff -u --recursive /scratch/install-axp/usr/src/egcs-1.1b/gcc/machmode.h egcs-1.1b-patched/gcc/machmode.h
--- /scratch/install-axp/usr/src/egcs-1.1b/gcc/machmode.h Mon Jul 6 18:17:36 1998
+++ egcs-1.1b-patched/gcc/machmode.h Mon Feb 22 21:00:07 1999
@@ -39,15 +39,18 @@
/* Find the largest host integer type and set its size and type. */
#ifndef HOST_BITS_PER_WIDE_INT
-
-#if HOST_BITS_PER_LONG > HOST_BITS_PER_INT
-#define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG
-#define HOST_WIDE_INT long
-#else
-#define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT
-#define HOST_WIDE_INT int
-#endif
-
+ #if HOST_BITS_PER_LONGLONG > HOST_BITS_PER_INT && HOST_BITS_PER_LONGLONG > HOST_BITS_PER_LONG
+ #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONGLONG
+ #define HOST_WIDE_INT long long
+ #else
+ #if HOST_BITS_PER_LONG > HOST_BITS_PER_INT
+ #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG
+ #define HOST_WIDE_INT long
+ #else
+ #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT
+ #define HOST_WIDE_INT int
+ #endif
+ #endif
#endif
/* Provide a default way to print an address in hex via printf. */
------------------------------------------------------------------------------
To prevent the cross-gcc from segfaulting I also had to make the folluwing
casts to constant integers.
The reason is that I found out that some constant function arguments were
passed as 32-bit integers where they are assumed to be HOST_WIDE_INT (and thus
long long = 64-bit). Maybe some casts are superfluous but they shouldn't harm.
egcs seems to work now. I was able to sucessfully compile a linux-kernel, bash,
glibc, ncurses, binutils and egcs itself for the alpha.
I hope you can use this information.
Thank you.
Thorsten Kranzkowski
------------------------------------------------------------------------------
diff -u --recursive /scratch/install-axp/usr/src/egcs-1.1b/gcc/config/alpha/alpha.c egcs-1.1b-patched/gcc/config/alpha/alpha.c
--- /scratch/install-axp/usr/src/egcs-1.1b/gcc/config/alpha/alpha.c Mon Jul 6 23:32:38 1998
+++ egcs-1.1b-patched/gcc/config/alpha/alpha.c Mon Feb 22 23:42:53 1999
@@ -336,7 +336,7 @@
enum machine_mode mode;
{
return ((GET_CODE (op) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
+ && (unsigned HOST_WIDE_INT) INTVAL (op) < (unsigned HOST_WIDE_INT)64)
|| GET_CODE (op) == CONSTANT_P_RTX
|| register_operand (op, mode));
}
@@ -350,7 +350,7 @@
enum machine_mode mode;
{
return ((GET_CODE (op) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
+ && (unsigned HOST_WIDE_INT) INTVAL (op) < (unsigned HOST_WIDE_INT)0x100)
|| GET_CODE (op) == CONSTANT_P_RTX
|| register_operand (op, mode));
}
@@ -363,7 +363,7 @@
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return ((GET_CODE (op) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
+ && (unsigned HOST_WIDE_INT) INTVAL (op) < (unsigned HOST_WIDE_INT)0x100)
|| GET_CODE (op) == CONSTANT_P_RTX);
}
@@ -393,8 +393,8 @@
enum machine_mode mode;
{
if (GET_CODE (op) == CONST_INT)
- return ((unsigned HOST_WIDE_INT) INTVAL (op) < 255
- || (unsigned HOST_WIDE_INT) (- INTVAL (op)) < 255);
+ return ((unsigned HOST_WIDE_INT) INTVAL (op) < (unsigned HOST_WIDE_INT)255
+ || (unsigned HOST_WIDE_INT) (- INTVAL (op)) < (unsigned HOST_WIDE_INT)255);
else if (GET_CODE (op) == CONSTANT_P_RTX)
return 1;
@@ -424,8 +424,8 @@
&& zap_mask (CONST_DOUBLE_HIGH (op)));
if (GET_CODE (op) == CONST_INT)
- return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
- || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
+ return ((unsigned HOST_WIDE_INT) INTVAL (op) < (unsigned HOST_WIDE_INT)0x100
+ || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < (unsigned HOST_WIDE_INT)0x100
|| zap_mask (INTVAL (op)));
else if (GET_CODE (op) == CONSTANT_P_RTX)
return 1;
@@ -441,8 +441,8 @@
enum machine_mode mode;
{
if (GET_CODE (op) == CONST_INT)
- return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
- || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
+ return ((unsigned HOST_WIDE_INT) INTVAL (op) < (unsigned HOST_WIDE_INT)0x100
+ || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < (unsigned HOST_WIDE_INT)0x100);
else if (GET_CODE (op) == CONSTANT_P_RTX)
return 1;
@@ -485,7 +485,7 @@
|| INTVAL (op) == 0xffff
|| INTVAL (op) == 0xffffffff
#if HOST_BITS_PER_WIDE_INT == 64
- || INTVAL (op) == 0xffffffffffffffff
+ || (unsigned HOST_WIDE_INT)INTVAL (op) == (unsigned HOST_WIDE_INT)0xffffffffffffffff
#endif
));
}
@@ -498,7 +498,7 @@
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return (GET_CODE (op) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
+ && (unsigned HOST_WIDE_INT) INTVAL (op) < (unsigned HOST_WIDE_INT)64
&& (INTVAL (op) & 7) == 0);
}
@@ -1146,7 +1146,7 @@
- floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
for (; bits > 0; bits--)
if ((temp = alpha_emit_set_const (subtarget, mode,
- c << bits, i)) != 0
+ (unsigned HOST_WIDE_INT) c << bits, i)) != 0
|| ((temp = (alpha_emit_set_const
(subtarget, mode,
((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
@@ -1163,10 +1163,11 @@
- floor_log2 (~ c) - 2)) > 0)
for (; bits > 0; bits--)
if ((temp = alpha_emit_set_const (subtarget, mode,
- c << bits, i)) != 0
+ (unsigned HOST_WIDE_INT) c << bits, i)) != 0
|| ((temp = (alpha_emit_set_const
(subtarget, mode,
- ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
+ (( (unsigned HOST_WIDE_INT)c << bits) |
+ (((HOST_WIDE_INT) 1 << bits) - 1)),
i)))
!= 0))
return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
@@ -1590,7 +1591,7 @@
#if HOST_BITS_PER_WIDE_INT == 32
rtx msk = immed_double_const (0xffffffff, 0xffffffff, DImode);
#else
- rtx msk = immed_double_const (0xffffffffffffffff, 0, DImode);
+ rtx msk = immed_double_const ((HOST_WIDE_INT)0xffffffffffffffff, 0, DImode);
#endif
emit_insn (gen_mskxl (dstl, dstl, msk, addr));
}
@@ -1700,7 +1701,7 @@
#if HOST_BITS_PER_WIDE_INT == 32
rtx const im1 = immed_double_const (0xffffffff, 0xffffffff, DImode);
#else
- rtx const im1 = immed_double_const (0xffffffffffffffff, 0, DImode);
+ rtx const im1 = immed_double_const ((HOST_WIDE_INT)0xffffffffffffffff, 0, DImode);
#endif
rtx ins_tmps[MAX_MOVE_WORDS];
rtx st_tmp_1, st_tmp_2, dreg;
@@ -1797,8 +1798,8 @@
rtx orig_dst = operands[0];
rtx data_regs[2*MAX_MOVE_WORDS+16];
rtx tmp;
- int i, words, ofs, nregs = 0;
-
+ int i, nregs = 0;
+ HOST_WIDE_INT words,ofs ;
if (bytes <= 0)
return 1;
if (bytes > MAX_MOVE_WORDS*8)
@@ -1934,14 +1935,14 @@
if (!TARGET_BWX && bytes >= 8)
{
data_regs[nregs++] = tmp = gen_reg_rtx (DImode);
- alpha_expand_unaligned_load (tmp, orig_src, 8, ofs, 0);
+ alpha_expand_unaligned_load (tmp, orig_src, (HOST_WIDE_INT) 8, ofs, 0);
bytes -= 8;
ofs += 8;
}
if (!TARGET_BWX && bytes >= 4)
{
data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
- alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
+ alpha_expand_unaligned_load (tmp, orig_src, (HOST_WIDE_INT) 4, ofs, 0);
bytes -= 4;
ofs += 4;
}
@@ -1962,7 +1963,7 @@
else if (!TARGET_BWX)
{
data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
- alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
+ alpha_expand_unaligned_load (tmp, orig_src, (HOST_WIDE_INT) 2, ofs, 0);
bytes -= 2;
ofs += 2;
}
@@ -2061,7 +2062,7 @@
break;
if (words == 1)
- alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
+ alpha_expand_unaligned_store (orig_dst, data_regs[i], (HOST_WIDE_INT)8, ofs);
else
alpha_expand_unaligned_store_words (data_regs+i, orig_dst, words, ofs);
@@ -2074,7 +2075,7 @@
words in registers and using alpha_expand_unaligned_store_words. */
while (i < nregs && GET_MODE (data_regs[i]) == SImode)
{
- alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
+ alpha_expand_unaligned_store (orig_dst, data_regs[i], (HOST_WIDE_INT)4, ofs);
ofs += 4;
i++;
}
@@ -2092,7 +2093,7 @@
else
while (i < nregs && GET_MODE (data_regs[i]) == HImode)
{
- alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
+ alpha_expand_unaligned_store (orig_dst, data_regs[i], (HOST_WIDE_INT)2, ofs);
i++;
ofs += 2;
}
@@ -2203,13 +2204,13 @@
if (!TARGET_BWX && bytes >= 8)
{
- alpha_expand_unaligned_store (orig_dst, const0_rtx, 8, ofs);
+ alpha_expand_unaligned_store (orig_dst, const0_rtx, (HOST_WIDE_INT)8, ofs);
bytes -= 8;
ofs += 8;
}
if (!TARGET_BWX && bytes >= 4)
{
- alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
+ alpha_expand_unaligned_store (orig_dst, const0_rtx, (HOST_WIDE_INT)4, ofs);
bytes -= 4;
ofs += 4;
}
@@ -2228,7 +2229,7 @@
}
else if (!TARGET_BWX)
{
- alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
+ alpha_expand_unaligned_store (orig_dst, const0_rtx,(HOST_WIDE_INT) 2, ofs);
bytes -= 2;
ofs += 2;
}
@@ -2724,7 +2725,7 @@
&& CONST_DOUBLE_LOW (x) == -1)
fprintf (file, "q");
#else
- else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffffffffffff)
+ else if (GET_CODE (x) == CONST_INT && INTVAL (x) == (HOST_WIDE_INT)0xffffffffffffffff)
fprintf (file, "q");
else if (GET_CODE (x) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (x) == 0
diff -u --recursive /scratch/install-axp/usr/src/egcs-1.1b/gcc/config/alpha/alpha.md egcs-1.1b-patched/gcc/config/alpha/alpha.md
--- /scratch/install-axp/usr/src/egcs-1.1b/gcc/config/alpha/alpha.md Thu Jul 30 19:12:16 1998
+++ egcs-1.1b-patched/gcc/config/alpha/alpha.md Mon Feb 22 23:50:42 1999
@@ -4221,7 +4221,7 @@
else if (GET_CODE (operands[1]) == CONST_INT)
{
operands[1]
- = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
+ = alpha_emit_set_const (operands[0], SImode, ( HOST_WIDE_INT) INTVAL (operands[1]), 3);
if (rtx_equal_p (operands[0], operands[1]))
DONE;
}
@@ -4238,7 +4238,7 @@
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
"
{ rtx tem
- = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
+ = alpha_emit_set_const (operands[0], SImode, (HOST_WIDE_INT) INTVAL (operands[1]), 2);
if (tem == operands[0])
DONE;
@@ -4309,7 +4309,7 @@
;
else if (GET_CODE (operands[1]) == CONST_INT
&& (tem = alpha_emit_set_const (operands[0], DImode,
- INTVAL (operands[1]), 3)) != 0)
+ (HOST_WIDE_INT) INTVAL (operands[1]), 3)) != 0)
{
if (rtx_equal_p (tem, operands[0]))
DONE;
@@ -4367,7 +4367,7 @@
(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
"
{ rtx tem
- = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
+ = alpha_emit_set_const (operands[0], DImode, (HOST_WIDE_INT) INTVAL (operands[1]), 2);
if (tem == operands[0])
DONE;
@@ -4525,7 +4525,7 @@
&& ! input_operand (operands[1], QImode))
{
operands[1] = alpha_emit_set_const (operands[0], QImode,
- INTVAL (operands[1]), 3);
+ ( HOST_WIDE_INT) INTVAL (operands[1]), 3);
if (rtx_equal_p (operands[0], operands[1]))
DONE;
@@ -4636,7 +4636,7 @@
&& ! input_operand (operands[1], HImode))
{
operands[1] = alpha_emit_set_const (operands[0], HImode,
- INTVAL (operands[1]), 3);
+ (HOST_WIDE_INT) INTVAL (operands[1]), 3);
if (rtx_equal_p (operands[0], operands[1]))
DONE;
@@ -4883,8 +4883,8 @@
FAIL;
alpha_expand_unaligned_load (operands[0], operands[1],
- INTVAL (operands[2]) / 8,
- INTVAL (operands[3]) / 8, 1);
+ (HOST_WIDE_INT) INTVAL (operands[2]) / 8,
+ (HOST_WIDE_INT) INTVAL (operands[3]) / 8, 1);
DONE;
}")
@@ -4911,8 +4911,8 @@
FAIL;
alpha_expand_unaligned_load (operands[0], operands[1],
- INTVAL (operands[2]) / 8,
- INTVAL (operands[3]) / 8, 0);
+ (HOST_WIDE_INT) INTVAL (operands[2]) / 8,
+ (HOST_WIDE_INT) INTVAL (operands[3]) / 8, 0);
DONE;
}
}")
@@ -4938,8 +4938,8 @@
FAIL;
alpha_expand_unaligned_store (operands[0], operands[3],
- INTVAL (operands[1]) / 8,
- INTVAL (operands[2]) / 8);
+ (HOST_WIDE_INT) INTVAL (operands[1]) / 8,
+ (HOST_WIDE_INT) INTVAL (operands[2]) / 8);
DONE;
}")
------------------------------------------------------------------------------
--
| Thorsten Kranzkowski Snail: Niemannsweg 30, 49201 Dissen, Germany |
| Mobile: ++49 161 7210230 Inet: tkranzk@physik.uni-osnabrueck.de |
| Ampr: dl8bcu@db0nei.#nrw.deu.eu, dl8bcu@marvin.dl8bcu.ampr.org [44.130.8.19] |