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Re: gcc bugs with Mesa 2.6 source code on SGI Irix 6.2
- To: atai at ece dot ucsd dot edu (Andy Tai)
- Subject: Re: gcc bugs with Mesa 2.6 source code on SGI Irix 6.2
- From: Jim Wilson <wilson at cygnus dot com>
- Date: Tue, 19 May 1998 19:21:43 -0700
- cc: egcs-bugs at cygnus dot com, atai at ucsd dot edu
When I compile the latest stable version of Mesa (2.6), the OpenGL compatible
3d graphics library
gcc -c -I../include -pedantic -O2 triangle.c
triangle.c: In function `lambda_textured_triangle':
triangle.c:697: Non-optional registers need a spill register
(insn:QI 3046 3045 3047 (set (mem:DF (plus:SI (reg:SI 29 sp)
(const_int 35704)))
(reg:DF 55 $f23)) 193 {movdf_internal1} (nil)
(nil))
This seems to be a generic problem with gcc, in that it is unable to
reload a REG+LARGE_INT address to match an offsettable memory 'o' constraint.
We probably have to do something about that.
Meanwhile, it is easy to work around this problem in egcs, as we don't
actually need an offsettable mem in 64 bit code, since we can do this with
a single 64-bit load instruction. This will also give us better code,
so we want to do this anyways.
I see no easy way to workaround the problem in gcc2, unless I move a large
hunk of code from egcs to gcc2, so I am leaving this unfixed in gcc2 for now.
Tue May 19 19:08:52 1998 Jim Wilson <wilson@cygnus.com>
* config/mips/mips.c (double_memory_operand): Accept any MEM during
reload when TARGET_64BIT.
Index: config/mips/mips.c
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/mips/mips.c,v
retrieving revision 1.27
diff -p -r1.27 mips.c
*** mips.c 1998/05/06 16:21:01 1.27
--- mips.c 1998/05/13 04:01:20
*************** double_memory_operand (op, mode)
*** 807,812 ****
--- 807,823 ----
&& double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
return 1;
+ /* All reloaded addresses are valid in TARGET_64BIT mode. This is
+ the same test performed for 'm' in find_reloads. */
+
+ if (reload_in_progress
+ && TARGET_64BIT
+ && (GET_CODE (op) == MEM
+ || (GET_CODE (op) == REG
+ && REGNO (op) >= FIRST_PSEUDO_REGISTER
+ && reg_renumber[REGNO (op)] < 0)))
+ return 1;
+
if (reload_in_progress
&& TARGET_MIPS16
&& GET_CODE (op) == MEM)