This is the mail archive of the
java-patches@gcc.gnu.org
mailing list for the Java project.
[Patch] libffi-MIPS: More n64 fixes.
- From: David Daney <ddaney at avtrex dot com>
- To: Java Patch List <java-patches at gcc dot gnu dot org>, gcc-patches <gcc-patches at gcc dot gnu dot org>, Richard Sandiford <rsandifo at nildram dot co dot uk>
- Date: Fri, 07 Dec 2007 00:01:53 -0800
- Subject: [Patch] libffi-MIPS: More n64 fixes.
As with my patch from yesterday, this patch fixes several failures in
the libffi testsuite caused by the use of a 32 bit add instruction on a
64 bit pointer value causing the upper 32 bits to be clobbered. At the
same time I took the liberty of converting several 'add a,b,0' to 'move
a,b'. Although these were not causing any immediate problems, I think
it makes the code more understandable.
Tested on mips64-unknown-linux-gnu both n32 and n64 ABIs.
OK to commit?
2007-12-07 David Daney <ddaney@avtrex.com>
* src/mips/n32.S (ffi_call_N32): Replace dadd with ADDU, dsub with
SUBU, add with ADDU and 'add a,b,0' with 'move a,b' throughout.
Index: n32.S
===================================================================
--- n32.S (revision 130659)
+++ n32.S (working copy)
@@ -96,16 +96,16 @@ sixteen:
REG_L t6, 2*FFI_SIZEOF_ARG($fp)
# Is it bigger than 8 * FFI_SIZEOF_ARG?
- dadd t7, $0, 8 * FFI_SIZEOF_ARG
- dsub t8, t6, t7
+ ADDU t7, $0, 8 * FFI_SIZEOF_ARG
+ SUBU t8, t6, t7
bltz t8, loadregs
- add t9, t9, t8
+ ADDU t9, t9, t8
loadregs:
REG_L t4, 3*FFI_SIZEOF_ARG($fp) # load the flags word
- add t6, t4, 0 # and copy it into t6
+ move t6, t4 # and copy it into t6
and t4, ((1<<FFI_FLAG_BITS)-1)
bnez t4, arg1_floatp
@@ -119,7 +119,7 @@ arg1_doublep:
l.d $f12, 0*FFI_SIZEOF_ARG(t9)
arg1_next:
- add t4, t6, 0
+ move t4, t6
SRL t4, 1*FFI_FLAG_BITS
and t4, ((1<<FFI_FLAG_BITS)-1)
bnez t4, arg2_floatp
@@ -133,7 +133,7 @@ arg2_doublep:
l.d $f13, 1*FFI_SIZEOF_ARG(t9)
arg2_next:
- add t4, t6, 0
+ move t4, t6
SRL t4, 2*FFI_FLAG_BITS
and t4, ((1<<FFI_FLAG_BITS)-1)
bnez t4, arg3_floatp
@@ -147,7 +147,7 @@ arg3_doublep:
l.d $f14, 2*FFI_SIZEOF_ARG(t9)
arg3_next:
- add t4, t6, 0
+ move t4, t6
SRL t4, 3*FFI_FLAG_BITS
and t4, ((1<<FFI_FLAG_BITS)-1)
bnez t4, arg4_floatp
@@ -161,7 +161,7 @@ arg4_doublep:
l.d $f15, 3*FFI_SIZEOF_ARG(t9)
arg4_next:
- add t4, t6, 0
+ move t4, t6
SRL t4, 4*FFI_FLAG_BITS
and t4, ((1<<FFI_FLAG_BITS)-1)
bnez t4, arg5_floatp
@@ -175,7 +175,7 @@ arg5_doublep:
l.d $f16, 4*FFI_SIZEOF_ARG(t9)
arg5_next:
- add t4, t6, 0
+ move t4, t6
SRL t4, 5*FFI_FLAG_BITS
and t4, ((1<<FFI_FLAG_BITS)-1)
bnez t4, arg6_floatp
@@ -189,7 +189,7 @@ arg6_doublep:
l.d $f17, 5*FFI_SIZEOF_ARG(t9)
arg6_next:
- add t4, t6, 0
+ move t4, t6
SRL t4, 6*FFI_FLAG_BITS
and t4, ((1<<FFI_FLAG_BITS)-1)
bnez t4, arg7_floatp
@@ -203,7 +203,7 @@ arg7_doublep:
l.d $f18, 6*FFI_SIZEOF_ARG(t9)
arg7_next:
- add t4, t6, 0
+ move t4, t6
SRL t4, 7*FFI_FLAG_BITS
and t4, ((1<<FFI_FLAG_BITS)-1)
bnez t4, arg8_floatp