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Re: ARM: enable interpreter, add locks code

From: David Daney <ddaney at avtrex dot com>
To: David Daney <ddaney at avtrex dot com>, Andrew Haley <aph-gcc at littlepinkcloud dot COM>, java-patches at gcc dot gnu dot org, gcc-patches at gcc dot gnu dot org
Date: Wed, 11 Jul 2007 14:59:32 -0700
Subject: Re: ARM: enable interpreter, add locks code
References: <18069.10098.18740.585534@zebedee.pink> <46953664.8070205@avtrex.com> <20070711214757.GA12028@caradoc.them.org>

Daniel Jacobowitz wrote:

On Wed, Jul 11, 2007 at 12:58:28PM -0700, David Daney wrote:

Andrew Haley wrote:

+/* Atomic compare and exchange.  These sequences are not actually
+   atomic; there is a race if *ADDR != OLD_VAL and we are preempted
+   between the two swaps.  However, they are very close to atomic, and
+   are the best that a pre-ARMv6 implementation can do without
+   operating system support.  LinuxThreads has been using these
+   sequences for many years.  */

Wow! That is terrible.

Actually it works very well :-)

Until you get a random deadlock in a long running process.

It seems like the LinuxThreads bug for MIPS in glibc 2.2.5 that I spent about a week trying to figure out. At least in that case upgrading to glibc 2.3.3 fixed things nicely.

David Daney

References:
- ARM: enable interpreter, add locks code
  - From: Andrew Haley
- Re: ARM: enable interpreter, add locks code
  - From: David Daney
- Re: ARM: enable interpreter, add locks code
  - From: Daniel Jacobowitz

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