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Re: PATCH: Allow non-arithmetic type for pthread_t
- From: Bryce McKinlay <bryce at waitaki dot otago dot ac dot nz>
- To: rittle at labs dot mot dot com
- Cc: java-patches at gcc dot gnu dot org
- Date: Wed, 20 Mar 2002 14:55:59 +1200
- Subject: Re: PATCH: Allow non-arithmetic type for pthread_t
- References: <200203191627.g2JGRXk33208@latour.rsch.comm.mot.com>
Loren James Rittle wrote:
>However, I would like to observe an outright portability bug in this
>code with or without my proposed patch. If sizeof (obj_addr_t) >
>sizeof (pthread_t), then this code could blow up in various manners
>depending upon exact architectural properties.
>
Indeed! This patch ought to fix that. I will check it in to mainline and
branch.
regards
Bryce.
2002-03-20 Bryce McKinlay <bryce@waitaki.otago.ac.nz>
* posix-threads.cc (_Jv_ThreadSelf_out_of_line): Use write_barrier,
not release_set.
* sysdep/powerpc/locks.h (write_barrier): New function.
* sysdep/i386/locks.h (write_barrier): New function.
Index: posix-threads.cc
===================================================================
RCS file: /cvs/gcc/gcc/libjava/posix-threads.cc,v
retrieving revision 1.31
diff -u -r1.31 posix-threads.cc
--- posix-threads.cc 2002/03/10 03:53:12 1.31
+++ posix-threads.cc 2002/03/20 02:53:27
@@ -448,7 +448,8 @@
{
pthread_t self = pthread_self();
sce -> high_sp_bits = high_sp_bits;
- release_set ((obj_addr_t *) &(sce -> self), self);
+ write_barrier();
+ sce -> self = self;
return self;
}
Index: sysdep/powerpc/locks.h
===================================================================
RCS file: /cvs/gcc/gcc/libjava/sysdep/powerpc/locks.h,v
retrieving revision 1.1
diff -u -r1.1 locks.h
--- locks.h 2002/03/10 03:31:08 1.1
+++ locks.h 2002/03/20 02:53:27
@@ -75,4 +75,12 @@
__asm__ __volatile__ ("isync" : : : "memory");
}
+// Ensure that prior stores to memory are completed with respect to other
+// processors.
+inline static void
+write_barrier()
+{
+ __asm__ __volatile__ ("sync" : : : "memory");
+}
+
#endif
Index: sysdep/i386/locks.h
===================================================================
RCS file: /cvs/gcc/gcc/libjava/sysdep/i386/locks.h,v
retrieving revision 1.1
diff -u -r1.1 locks.h
--- locks.h 2002/03/10 03:31:05 1.1
+++ locks.h 2002/03/20 02:53:27
@@ -62,4 +62,12 @@
{
}
+// Ensure that prior stores to memory are completed with respect to other
+// processors.
+inline static void
+write_barrier()
+{
+ // X86 does not reorder writes. We just need to ensure that gcc also doesn't.
+ __asm__ __volatile__(" " : : : "memory");
+}
#endif