This is the mail archive of the
java-patches@gcc.gnu.org
mailing list for the Java project.
Java: hashtable synchronization for PowerPC
- From: Bryce McKinlay <bryce at waitaki dot otago dot ac dot nz>
- To: java-patches at gcc dot gnu dot org, gcc-patches at gcc dot gnu dot org, "Boehm, Hans" <hans_boehm at hp dot com>
- Date: Sun, 03 Mar 2002 16:58:58 +1300
- Subject: Java: hashtable synchronization for PowerPC
This patch effects the Java front end, libjava, and boehm-gc. It enables
hashtable locks on PowerPC, and cleans up libjava's synchronization
primitives into sysdeps header files rather than making natObject.cc too
huge. Maybe eventually we can share these between boehm-gc and libjava
and anything else that needs them.
This results in a moderate slowdown of synchronization performance on my
tests, but also improves gctest performance significantly, and reduces
memory usage, so hopefully the overall effect will be a net win (also
the hash sync code has a lot of assertions which are not yet disabled,
so it should speed up some more when I fix that).
Using SLOW_PTHREAD_SELF is definatly a win for PowerPC as the
pthread_self implementation in glibc uses the very slow default/fallback
code. This has to traverse a thread chain in order to determine thread
ID, so I imagine that the gap will increase further with a large number
of threads.
I added an "isync" instruction as a read barrier for _Jv_ThreadSelf.
Although the programming environments manual makes no mention of isync
being required to enforce ordering of data reads on multiprocessors, the
compare and swap implementation in glibc uses it, and I came across this
message which argues that it is necccessary:
http://sources.redhat.com/ml/libc-alpha/2001-05/msg00029.html
The "isync" does slow down the hash lookup substantially on my powerbook
(mpc7410), but it is still a lot faster than using PPC pthread_self.
Look ok?
regards
Bryce.
gcc/java:
2002-03-03 Bryce McKinlay <bryce@waitaki.otago.ac.nz>
* decl.c (java_init_decl_processing): Make sure class_type_node
alignment is not less than 8 byte if hash synchronization is enabled.
boehm-gc:
2002-03-03 Bryce McKinlay <bryce@waitaki.otago.ac.nz>
* include/private/gc_priv.h: Set DOUBLE_ALIGNMENT if target alignment
is < 8 bytes and GCJ support is enabled.
libjava:
2002-03-03 Bryce McKinlay <bryce@waitaki.otago.ac.nz>
* configure.in: Define SLOW_PTHREAD_SELF if configure.host set
slow_pthread_self. Set up symlink for sysdeps directory.
* configure.host: Document more shell variables. Set sysdeps_dir
for most platforms. Set slow_pthread_self for i686. Set
enable_hash_synchronization_default and slow_pthread_self for PowerPC.
* posix-threads.cc (_Jv_ThreadSelf_out_of_line): Use release_set so
that memory barrier is emitted where required.
* include/posix-threads.h (_Jv_ThreadSelf for SLOW_PTHREAD_SELF): Add
read_barrier() to enforce ordering of reads.
* sysdep/powerpc/locks.h: New file. Implementation of synchronization
primitives for PowerPC.
* sysdep/i386/locks.h: New file. Synchronization primitives for i386
moved from natObject.cc.
* sysdep/alpha/locks.h: Likewise.
* sysdep/ia64/locks.h: Likewise.
* sysdep/generic/locks.h: Likewise.
* java/lang/natObject.cc: Move thread synchronization primitives to
system-dependent headers.
Index: decl.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/java/decl.c,v
retrieving revision 1.119
diff -u -r1.119 decl.c
--- decl.c 2002/02/28 07:39:42 1.119
+++ decl.c 2002/03/03 03:01:05
@@ -680,6 +681,10 @@
for (t = TYPE_FIELDS (class_type_node); t != NULL_TREE; t = TREE_CHAIN (t))
FIELD_PRIVATE (t) = 1;
push_super_field (class_type_node, object_type_node);
+
+ /* Hash synchronization requires at least double-word alignment. */
+ if (flag_hash_synchronization && POINTER_SIZE < 64)
+ TYPE_ALIGN (class_type_node) = 64;
FINISH_RECORD (class_type_node);
build_decl (TYPE_DECL, get_identifier ("Class"), class_type_node);
Index: include/private/gc_priv.h
===================================================================
RCS file: /cvs/gcc/egcs/boehm-gc/include/private/gc_priv.h,v
retrieving revision 1.6
diff -u -r1.6 gc_priv.h
--- gc_priv.h 2002/02/12 04:37:57 1.6
+++ gc_priv.h 2002/03/03 03:19:52
@@ -205,6 +205,12 @@
/* odd numbered words to have mark bits. */
#endif
+#if defined(GC_GCJ_SUPPORT) && ALIGNMENT < 8 && !defined(ALIGN_DOUBLE)
+ /* GCJ's Hashtable synchronization code requires 64-bit alignment. */
+# define ALIGN_DOUBLE
+#endif
+
+
/* ALIGN_DOUBLE requires MERGE_SIZES at present. */
# if defined(ALIGN_DOUBLE) && !defined(MERGE_SIZES)
# define MERGE_SIZES
Index: configure.in
===================================================================
RCS file: /cvs/gcc/egcs/libjava/configure.in,v
retrieving revision 1.115
diff -u -r1.115 configure.in
--- configure.in 2002/02/27 05:32:13 1.115
+++ configure.in 2002/03/03 03:09:37
@@ -83,6 +83,12 @@
enable_hash_synchronization=$enable_hash_synchronization_default
fi
+dnl configure.host sets slow_pthread_self if the synchronization code should
+dnl try to avoid pthread_self calls by caching thread IDs in a hashtable.
+if test "${slow_pthread_self}" = "yes"; then
+ AC_DEFINE(SLOW_PTHREAD_SELF)
+fi
+
dnl See if the user has requested runtime debugging.
LIBGCJDEBUG="false"
@@ -421,6 +427,8 @@
AC_SUBST(THREADDEPS)
AC_SUBST(THREADOBJS)
AC_SUBST(THREADSPEC)
+
+AC_LINK_FILES(sysdep/$sysdeps_dir, sysdep)
HASH_SYNC_SPEC=
# Hash synchronization is only useful with posix threads right now.
Index: configure.host
===================================================================
RCS file: /cvs/gcc/egcs/libjava/configure.host,v
retrieving revision 1.23
diff -u -r1.23 configure.host
--- configure.host 2002/02/08 14:46:36 1.23
+++ configure.host 2002/03/03 03:09:37
@@ -18,6 +18,14 @@
# libgcj_cflags Special CFLAGS to use when building
# libgcj_cxxflags Special CXXFLAGS to use when building
# libgcj_javaflags Special JAVAFLAGS to use when building
+# libgcj_interpreter If the bytecode interpreter supports this platform.
+# enable_java_net_default If java.net native code should be enabled by
+# default.
+# enable_hash_synchronization_default If hash synchronization should be
+# enabled by default.
+# sysdeps_dir Directory containing system-dependent headers
+# slow_pthread_self The synchronization code should try to avoid
+# pthread_self calls by caching thread IDs in a hashtable
libgcj_flags=
libgcj_cflags=
@@ -26,6 +34,8 @@
libgcj_interpreter=
enable_java_net_default=yes
enable_hash_synchronization_default=no
+sysdeps_dir=generic
+slow_pthread_self=
case "${target_optspace}:${host}" in
yes:*)
@@ -60,27 +70,35 @@
enable_getenv_properties_default=no
;;
i686-*|i586-*|i486-*|i386-*)
+ sysdeps_dir=i386
libgcj_flags="${libgcj_flags} -ffloat-store"
libgcj_interpreter=yes
libgcj_cxxflags="-D__NO_MATH_INLINES"
libgcj_cflags="-D__NO_MATH_INLINES"
DIVIDESPEC=-fno-use-divide-subroutine
enable_hash_synchronization_default=yes
+ slow_pthread_self=yes
;;
alpha*-*)
+ sysdeps_dir=alpha
libgcj_flags="${libgcj_flags} -mieee"
libgcj_interpreter=yes
enable_hash_synchronization_default=yes
;;
powerpc*-linux*)
+ sysdeps_dir=powerpc
libgcj_interpreter=yes
+ enable_hash_synchronization_default=yes
+ slow_pthread_self=yes
;;
- powerpc-apple-*)
+ powerpc*-darwin*)
+ sysdeps_dir=powerpc
libgcj_interpreter=no
;;
sparc-*)
;;
ia64-*)
+ sysdeps_dir=ia64
libgcj_flags="${libgcj_flags} -funwind-tables"
libgcj_interpreter=yes
enable_hash_synchronization_default=yes
Index: posix-threads.cc
===================================================================
RCS file: /cvs/gcc/egcs/libjava/posix-threads.cc,v
retrieving revision 1.30
diff -u -r1.30 posix-threads.cc
--- posix-threads.cc 2001/10/31 00:48:15 1.30
+++ posix-threads.cc 2002/03/03 03:09:37
@@ -438,19 +438,17 @@
#if defined(SLOW_PTHREAD_SELF)
-// Support for pthread_self() lookup cache.
+#include "sysdep/locks.h"
+// Support for pthread_self() lookup cache.
volatile self_cache_entry _Jv_self_cache[SELF_CACHE_SIZE];
-
_Jv_ThreadId_t
_Jv_ThreadSelf_out_of_line(volatile self_cache_entry *sce, size_t high_sp_bits)
{
pthread_t self = pthread_self();
- // The ordering between the following writes matters.
- // On Alpha, we probably need a memory barrier in the middle.
sce -> high_sp_bits = high_sp_bits;
- sce -> self = self;
+ release_set ((obj_addr_t *) &(sce -> self), self);
return self;
}
Index: sysdep/i386/locks.h
===================================================================
RCS file: locks.h
diff -N locks.h
--- /dev/null Tue May 5 13:32:27 1998
+++ locks.h Sat Mar 2 19:09:37 2002
@@ -0,0 +1,65 @@
+// locks.h - Thread synchronization primitives. X86 implementation.
+
+/* Copyright (C) 2002 Free Software Foundation
+
+ This file is part of libgcj.
+
+This software is copyrighted work licensed under the terms of the
+Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
+details. */
+
+#ifndef __SYSDEP_LOCKS_H__
+#define __SYSDEP_LOCKS_H__
+
+typedef size_t obj_addr_t; /* Integer type big enough for object */
+ /* address. */
+
+// Atomically replace *addr by new_val if it was initially equal to old.
+// Return true if the comparison succeeded.
+// Assumed to have acquire semantics, i.e. later memory operations
+// cannot execute before the compare_and_swap finishes.
+inline static bool
+compare_and_swap(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ char result;
+ __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
+ : "+m"(*(addr)), "=q"(result)
+ : "r" (new_val), "a"(old)
+ : "memory");
+ return (bool) result;
+}
+
+// Set *addr to new_val with release semantics, i.e. making sure
+// that prior loads and stores complete before this
+// assignment.
+// On X86, the hardware shouldn't reorder reads and writes,
+// so we just have to convince gcc not to do it either.
+inline static void
+release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
+{
+ __asm__ __volatile__(" " : : : "memory");
+ *(addr) = new_val;
+}
+
+// Compare_and_swap with release semantics instead of acquire semantics.
+// On many architecture, the operation makes both guarantees, so the
+// implementation can be the same.
+inline static bool
+compare_and_swap_release(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ return compare_and_swap(addr, old, new_val);
+}
+
+// Ensure that subsequent instructions do not execute on stale
+// data that was loaded from memory before the barrier.
+// On X86, the hardware ensures that reads are properly ordered.
+inline static void
+read_barrier()
+{
+}
+
+#endif
Index: sysdep/powerpc/locks.h
===================================================================
RCS file: locks.h
diff -N locks.h
--- /dev/null Tue May 5 13:32:27 1998
+++ locks.h Sat Mar 2 19:09:37 2002
@@ -0,0 +1,78 @@
+// locks.h - Thread synchronization primitives. PowerPC implementation.
+
+/* Copyright (C) 2002 Free Software Foundation
+
+ This file is part of libgcj.
+
+This software is copyrighted work licensed under the terms of the
+Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
+details. */
+
+#ifndef __SYSDEP_LOCKS_H__
+#define __SYSDEP_LOCKS_H__
+
+typedef size_t obj_addr_t; /* Integer type big enough for object */
+ /* address. */
+
+inline static bool
+compare_and_swap(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "0: lwarx %0,0,%1 ;"
+ " xor. %0,%3,%0;"
+ " bne 1f;"
+ " stwcx. %2,0,%1;"
+ " bne- 0b;"
+ "1: "
+ : "=&r"(ret)
+ : "r"(addr), "r"(new_val), "r"(old)
+ : "cr0", "memory");
+ /* This version of __compare_and_swap is to be used when acquiring
+ a lock, so we don't need to worry about whether other memory
+ operations have completed, but we do need to be sure that any loads
+ after this point really occur after we have acquired the lock. */
+ __asm__ __volatile__ ("isync" : : : "memory");
+ return ret == 0;
+}
+
+inline static void
+release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
+{
+ __asm__ __volatile__ ("sync" : : : "memory");
+ *(addr) = new_val;
+}
+
+inline static bool
+compare_and_swap_release(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ int ret;
+
+ __asm__ __volatile__ ("sync" : : : "memory");
+ __asm__ __volatile__ (
+ "0: lwarx %0,0,%1 ;"
+ " xor. %0,%3,%0;"
+ " bne 1f;"
+ " stwcx. %2,0,%1;"
+ " bne- 0b;"
+ "1: "
+ : "=&r"(ret)
+ : "r"(addr), "r"(new_val), "r"(old)
+ : "cr0", "memory");
+ return ret == 0;
+}
+
+// Ensure that subsequent instructions do not execute on stale
+// data that was loaded from memory before the barrier.
+inline static void
+read_barrier()
+{
+ __asm__ __volatile__ ("isync" : : : "memory");
+}
+
+#endif
Index: sysdep/alpha/locks.h
===================================================================
RCS file: locks.h
diff -N locks.h
--- /dev/null Tue May 5 13:32:27 1998
+++ locks.h Sat Mar 2 19:09:37 2002
@@ -0,0 +1,53 @@
+// locks.h - Thread synchronization primitives. Alpha implementation.
+
+/* Copyright (C) 2002 Free Software Foundation
+
+ This file is part of libgcj.
+
+This software is copyrighted work licensed under the terms of the
+Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
+details. */
+
+#ifndef __SYSDEP_LOCKS_H__
+#define __SYSDEP_LOCKS_H__
+
+typedef size_t obj_addr_t; /* Integer type big enough for object */
+ /* address. */
+
+inline static bool
+compare_and_swap(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ unsigned long oldval;
+ char result;
+ __asm__ __volatile__(
+ "1:ldq_l %0, %1\n\t" \
+ "cmpeq %0, %5, %2\n\t" \
+ "beq %2, 2f\n\t" \
+ "mov %3, %0\n\t" \
+ "stq_c %0, %1\n\t" \
+ "bne %0, 2f\n\t" \
+ "br 1b\n\t" \
+ "2:mb"
+ : "=&r"(oldval), "=m"(*addr), "=&r"(result)
+ : "r" (new_val), "m"(*addr), "r"(old) : "memory");
+ return (bool) result;
+}
+
+inline static void
+release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
+{
+ __asm__ __volatile__("mb" : : : "memory");
+ *(addr) = new_val;
+}
+
+inline static bool
+compare_and_swap_release(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ return compare_and_swap(addr, old, new_val);
+}
+
+#endif
Index: sysdep/ia64/locks.h
===================================================================
RCS file: locks.h
diff -N locks.h
--- /dev/null Tue May 5 13:32:27 1998
+++ locks.h Sat Mar 2 19:09:37 2002
@@ -0,0 +1,50 @@
+// locks.h - Thread synchronization primitives. IA64 implementation.
+
+/* Copyright (C) 2002 Free Software Foundation
+
+ This file is part of libgcj.
+
+This software is copyrighted work licensed under the terms of the
+Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
+details. */
+
+#ifndef __SYSDEP_LOCKS_H__
+#define __SYSDEP_LOCKS_H__
+
+typedef size_t obj_addr_t; /* Integer type big enough for object */
+ /* address. */
+
+inline static bool
+compare_and_swap(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ unsigned long oldval;
+ __asm__ __volatile__("mov ar.ccv=%4 ;; cmpxchg8.acq %0=%1,%2,ar.ccv"
+ : "=r"(oldval), "=m"(*addr)
+ : "r"(new_val), "1"(*addr), "r"(old) : "memory");
+ return (oldval == old);
+}
+
+// The fact that *addr is volatile should cause the compiler to
+// automatically generate an st8.rel.
+inline static void
+release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
+{
+ __asm__ __volatile__(" " : : : "memory");
+ *(addr) = new_val;
+}
+
+inline static bool
+compare_and_swap_release(volatile obj_addr_t *addr,
+ obj_addr_t old,
+ obj_addr_t new_val)
+{
+ unsigned long oldval;
+ __asm__ __volatile__("mov ar.ccv=%4 ;; cmpxchg8.rel %0=%1,%2,ar.ccv"
+ : "=r"(oldval), "=m"(*addr)
+ : "r"(new_val), "1"(*addr), "r"(old) : "memory");
+ return (oldval == old);
+}
+
+#endif
Index: sysdep/generic/locks.h
===================================================================
RCS file: locks.h
diff -N locks.h
--- /dev/null Tue May 5 13:32:27 1998
+++ locks.h Sat Mar 2 19:09:37 2002
@@ -0,0 +1,11 @@
+// locks.h - Thread synchronization primitives. Generic implementation.
+
+/* Copyright (C) 2002 Free Software Foundation
+
+ This file is part of libgcj.
+
+This software is copyrighted work licensed under the terms of the
+Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
+details. */
+
+#error Thread synchronization primitives not implemented for this platform.
Index: java/lang/natObject.cc
===================================================================
RCS file: /cvs/gcc/egcs/libjava/java/lang/natObject.cc,v
retrieving revision 1.21
diff -u -r1.21 natObject.cc
--- natObject.cc 2002/01/25 02:53:37 1.21
+++ natObject.cc 2002/03/03 03:09:38
@@ -307,129 +307,8 @@
#include <unistd.h> // for usleep, sysconf.
#include <sched.h> // for sched_yield.
#include <gcj/javaprims.h>
+#include <sysdep/locks.h>
-typedef size_t obj_addr_t; /* Integer type big enough for object */
- /* address. */
-
-// The following should move to some standard place. Linux-threads
-// already defines roughly these, as do more recent versions of boehm-gc.
-// The problem is that neither exports them.
-
-#if defined(__GNUC__) && defined(__i386__)
- // Atomically replace *addr by new_val if it was initially equal to old.
- // Return true if the comparison succeeded.
- // Assumed to have acquire semantics, i.e. later memory operations
- // cannot execute before the compare_and_swap finishes.
- inline static bool
- compare_and_swap(volatile obj_addr_t *addr,
- obj_addr_t old,
- obj_addr_t new_val)
- {
- char result;
- __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
- : "+m"(*(addr)), "=q"(result)
- : "r" (new_val), "a"(old)
- : "memory");
- return (bool) result;
- }
-
- // Set *addr to new_val with release semantics, i.e. making sure
- // that prior loads and stores complete before this
- // assignment.
- // On X86, the hardware shouldn't reorder reads and writes,
- // so we just have to convince gcc not to do it either.
- inline static void
- release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
- {
- __asm__ __volatile__(" " : : : "memory");
- *(addr) = new_val;
- }
-
- // Compare_and_swap with release semantics instead of acquire semantics.
- // On many architecture, the operation makes both guarantees, so the
- // implementation can be the same.
- inline static bool
- compare_and_swap_release(volatile obj_addr_t *addr,
- obj_addr_t old,
- obj_addr_t new_val)
- {
- return compare_and_swap(addr, old, new_val);
- }
-#endif
-
-#if defined(__GNUC__) && defined(__ia64__) && SIZEOF_VOID_P == 8
- inline static bool
- compare_and_swap(volatile obj_addr_t *addr,
- obj_addr_t old,
- obj_addr_t new_val)
- {
- unsigned long oldval;
- __asm__ __volatile__("mov ar.ccv=%4 ;; cmpxchg8.acq %0=%1,%2,ar.ccv"
- : "=r"(oldval), "=m"(*addr)
- : "r"(new_val), "1"(*addr), "r"(old) : "memory");
- return (oldval == old);
- }
-
- // The fact that *addr is volatile should cause the compiler to
- // automatically generate an st8.rel.
- inline static void
- release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
- {
- __asm__ __volatile__(" " : : : "memory");
- *(addr) = new_val;
- }
-
- inline static bool
- compare_and_swap_release(volatile obj_addr_t *addr,
- obj_addr_t old,
- obj_addr_t new_val)
- {
- unsigned long oldval;
- __asm__ __volatile__("mov ar.ccv=%4 ;; cmpxchg8.rel %0=%1,%2,ar.ccv"
- : "=r"(oldval), "=m"(*addr)
- : "r"(new_val), "1"(*addr), "r"(old) : "memory");
- return (oldval == old);
- }
-#endif
-
-#if defined(__GNUC__) && defined(__alpha__)
- inline static bool
- compare_and_swap(volatile obj_addr_t *addr,
- obj_addr_t old,
- obj_addr_t new_val)
- {
- unsigned long oldval;
- char result;
- __asm__ __volatile__(
- "1:ldq_l %0, %1\n\t" \
- "cmpeq %0, %5, %2\n\t" \
- "beq %2, 2f\n\t" \
- "mov %3, %0\n\t" \
- "stq_c %0, %1\n\t" \
- "bne %0, 2f\n\t" \
- "br 1b\n\t" \
- "2:mb"
- : "=&r"(oldval), "=m"(*addr), "=&r"(result)
- : "r" (new_val), "m"(*addr), "r"(old) : "memory");
- return (bool) result;
- }
-
- inline static void
- release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
- {
- __asm__ __volatile__("mb" : : : "memory");
- *(addr) = new_val;
- }
-
- inline static bool
- compare_and_swap_release(volatile obj_addr_t *addr,
- obj_addr_t old,
- obj_addr_t new_val)
- {
- return compare_and_swap(addr, old, new_val);
- }
-#endif
-
// Try to determine whether we are on a multiprocessor, i.e. whether
// spinning may be profitable.
// This should really use a suitable autoconf macro.
@@ -452,7 +331,6 @@
{
__asm__ __volatile__("" : : "rm"(p) : "memory");
}
-
// Each hash table entry holds a single preallocated "lightweight" lock.
// In addition, it holds a chain of "heavyweight" locks. Lightweight
Index: include/posix-threads.h
===================================================================
RCS file: /cvs/gcc/egcs/libjava/include/posix-threads.h,v
retrieving revision 1.20
diff -u -r1.20 posix-threads.h
--- posix-threads.h 2001/07/23 03:51:16 1.20
+++ posix-threads.h 2002/03/03 03:09:39
@@ -221,14 +221,6 @@
// to threads.
-#ifdef __i386__
-
-#define SLOW_PTHREAD_SELF
- // Add a cache for pthread_self() if we don't have the thread
- // pointer in a register.
-
-#endif /* __i386__ */
-
#ifdef __ia64__
typedef size_t _Jv_ThreadId_t;
@@ -270,6 +262,8 @@
#if defined(SLOW_PTHREAD_SELF)
+#include "sysdep/locks.h"
+
typedef pthread_t _Jv_ThreadId_t;
// E.g. on X86 Linux, pthread_self() is too slow for our purpose.
@@ -321,7 +315,7 @@
unsigned h = SC_INDEX(sp);
volatile self_cache_entry *sce = _Jv_self_cache + h;
pthread_t candidate_self = sce -> self; // Read must precede following one.
- // Read barrier goes here, if needed.
+ read_barrier();
if (sce -> high_sp_bits == sp >> LOG_THREAD_SPACING)
{
// The sce -> self value we read must be valid. An intervening