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Re: Expansion of narrowing math built-ins into power instructions

> > > > [ Please don't top-post ]

(I delete everything under your signature, without looking, assuming you
just forgot to).

On Sat, Aug 31, 2019 at 12:48:42AM +0530, Tejas Joshi wrote:
> > For ISA 2.07 (Power 8) you don't have IEEE128 at all, not in hardware
> > that is.  I don't know if we'll want fadd support in the emulation
> > libraries ever; don't worry about it for now, anyway.
> What instructions would need to be expanded for FADDL (long double to
> float) and DADDL (long double to double) on power8 (ISA 2.07) and
> power9 (ISA 3.0) respectively, along with VSX? (Just as we expanded
> FADD to fadds and xsaddsp for vsx).

If long double is double, faddl is the same as fadd, and daddl is just
normal addition.

If long double is double-double, faddl can be done as fadd on the first
double precision component of both args, and daddl is just normal addition
of those.

If long double is IEEE QP, then it is more interesting :-)

daddl is
  xsaddqpo # add qp, with round to odd
  xscvqpdp # convert qp to dp

faddl is
  xsaddqpo  # add qp, with round to odd
  xscvqpdpo # convert qp to dp, with round to odd
  xsrsp     # convert dp to sp
    (single precision numbers are stored in double precision format, but
     this is rounded as single precision)

fadds is
  fadds ;  :-)

Both faddl and daddl are the sequences for Power9.  There are no instructions
for QP format on Power8; see libgcc/config/rs6000/t-float128 for how support
for the emulation QP math is built, if you are interested.


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