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Special Memory Constraint [was Re: Indirect memory addresses vs. lra]

On Thu, Aug 15, 2019 at 02:23:45PM -0400, Vladimir Makarov wrote:

     > I tried this solution earlier.  But unfortunately it makes things worse.  What happens is it libgcc cannot
     > even be built -- ICEs occur on a memory from  address reg insn such as:
     > (insn 117 2981 3697 5 (set (mem/f:PSI (plus:PSI (reg:PSI 1309)
     >                  (const_int 102 [0x66])) [3 fs_129(D)->pc+0 S4 A8])
     > 		        (reg:PSI 1310)) "/home/jmd/Source/GCC2/libgcc/unwind-dw2.c":977:9 96 {movpsi}
     I see.?? Then for the insn, you could try to create a pattern
     "memory,special memory constraint".?? The special memory constraint
     should satisfy only spilled pseudo (pseudo with reg_renumber == -1).?? I
     believe lra-constraints.c can spill the pseudo and the end you will have
     mem[disp1 + r8|r9|sp] = mem[disp1+sp].

You mean something like this:

(define_special_memory_constraint "a"
 "My special memory constraint"
 (match_operand 0 "my_special_predicate")

(define_predicate "my_special_predicate"
		    (match_operand 0 "memory_operand")
  debug_rtx (op);
  if (MEM_P (op))
    op = XEXP (op, 0);
    if (GET_CODE (op) == PLUS)
	op = XEXP (op, 0);
	if (REG_P (op))
	    fprintf (stderr, "Reg number is %d\n", REGNO (op));
	    if (REGNO (op) >= 0)
	      return false;
  return true;

When I use this I get lots of the following ICEs

     "internal compiler error: maximum number of generated reload insns per insn achieved (90)"

It seems logical to me that this would happen since the constraint is not going to match any
operand with resolved registers.  Thus it will continually reload.

... which makes me think I've probably misunderstood what you are saying.


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