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RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
- From: Peng Fan <peng dot fan at nxp dot com>
- To: Michael Matz <matz at suse dot de>
- Cc: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>, "james dot greenhalgh at arm dot com" <james dot greenhalgh at arm dot com>, "nd at arm dot com" <nd at arm dot com>, "jailhouse-dev at googlegroups dot com" <jailhouse-dev at googlegroups dot com>, "will dot deacon at arm dot com" <will dot deacon at arm dot com>, Catalin Marinas <catalin dot marinas at arm dot com>
- Date: Wed, 13 Feb 2019 14:42:39 +0000
- Subject: RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
- References: <DB7PR04MB4490342F0A0FE96668B25F3188660@DB7PR04MB4490.eurprd04.prod.outlook.com> <alpine.LSU.2.21.1902131425580.5354@wotan.suse.de>
Hi Michael,
> -----Original Message-----
> From: Michael Matz [mailto:matz@suse.de]
> Sent: 2019年2月13日 22:28
> To: Peng Fan <peng.fan@nxp.com>
> Cc: gcc@gcc.gnu.org; james.greenhalgh@arm.com; nd@arm.com;
> jailhouse-dev@googlegroups.com; will.deacon@arm.com; Catalin Marinas
> <catalin.marinas@arm.com>
> Subject: Re: Warning: unpredictable: identical transfer and status registers
> --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
>
> Hi,
>
> On Wed, 13 Feb 2019, Peng Fan wrote:
>
> > asm volatile (
> > "ldxr %3, %2\n\t"
> > "ands %1, %3, %4\n\t"
> > "b.ne 1f\n\t"
> > "orr %3, %3, %4\n\t"
> > "1:\n\t"
> > "stxr %w0, %3, %2\n\t"
> > "dmb ish\n\t"
> > : "=r" (ret), "=&r" (test),
> > "+Q" (*(volatile unsigned long *)addr),
> > "=r" (tmp)
> > : "r" (1ul << nr));
>
> As Andreas says, you need to add an early-clobber for op3 for correctness (to
> force it into a different register from op4). And you also need an
> early-clobber on op0 to force it into a different register from op2 (which for
> purposes of register assignment is an input operand holding an address).
So the fix should be the following, right?
do {
asm volatile (
"ldxr %3, %2\n\t"
"ands %1, %3, %4\n\t"
"b.ne 1f\n\t"
"orr %3, %3, %4\n\t"
"1:\n\t"
"stxr %w0, %3, %2\n\t"
"dmb ish\n\t"
: "=&r" (ret), "=&r" (test),
"+Q" (*(volatile unsigned long *)addr),
"=&r" (tmp)
: "r" (1ul << nr));
} while (ret);
Thanks,
Peng.
>
>
> Ciao,
> Michael.