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RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
- From: Peng Fan <peng dot fan at nxp dot com>
- To: Segher Boessenkool <segher at kernel dot crashing dot org>
- Cc: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>, "james dot greenhalgh at arm dot com" <james dot greenhalgh at arm dot com>, "nd at arm dot com" <nd at arm dot com>, "jailhouse-dev at googlegroups dot com" <jailhouse-dev at googlegroups dot com>, "will dot deacon at arm dot com" <will dot deacon at arm dot com>, Catalin Marinas <catalin dot marinas at arm dot com>
- Date: Wed, 13 Feb 2019 13:41:26 +0000
- Subject: RE: Warning: unpredictable: identical transfer and status registers --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
- References: <DB7PR04MB4490342F0A0FE96668B25F3188660@DB7PR04MB4490.eurprd04.prod.outlook.com> <20190213091052.GV14180@gate.crashing.org>
> -----Original Message-----
> From: jailhouse-dev@googlegroups.com
> [mailto:jailhouse-dev@googlegroups.com] On Behalf Of Segher Boessenkool
> Sent: 2019年2月13日 17:11
> To: Peng Fan <peng.fan@nxp.com>
> Cc: gcc@gcc.gnu.org; james.greenhalgh@arm.com; nd@arm.com;
> jailhouse-dev@googlegroups.com; will.deacon@arm.com; Catalin Marinas
> <catalin.marinas@arm.com>
> Subject: Re: Warning: unpredictable: identical transfer and status registers
> --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
>
> OneWed, Feb 13, 2019 at 07:13:21AM +0000, Peng Fan wrote:
> > We met an issue when building a piece jailhouse hypervisor code,
> "stxr %w0, %3, %2\n\t" is
> > compiled as "stxr w4,x5,[x4]" which triggers the warning
> > "Warning: unpredictable: identical transfer and status registers"
>
> This is not a GCC question.
>
> The three registers, in order, are status, transfer, and base. The warning
> claims transfer and status are identical, but in fact base and status are.
> The code (in binutils, gas/config/tc-aarch64.c) is
>
> case ldstexcl:
> /* It is unpredictable if the destination and status registers are the
> same. */
> if ((aarch64_get_operand_class (opnds[0].type)
> == AARCH64_OPND_CLASS_INT_REG)
> && (aarch64_get_operand_class (opnds[1].type)
> == AARCH64_OPND_CLASS_INT_REG)
> && (opnds[0].reg.regno == opnds[1].reg.regno
> || opnds[0].reg.regno == opnds[2].reg.regno))
> as_warn (_("unpredictable: identical transfer and status registers"
> " --`%s'"),
> str);
>
> so either that op0 == op2 test is spurious, or the warning message is
> misleading.
From aarch64 spec, "stxr w4,x5,[x4]"'s behavior is chip implementation defined,
so I think the warning is correct.
>
> Please ask on binutils@sourceware.org and/or file a bug at
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsour
> ceware.org%2Fbugzilla%2F&data=02%7C01%7Cpeng.fan%40nxp.com%
> 7C2463376de5aa417d3d6508d69197e4df%7C686ea1d3bc2b4c6fa92cd99c5c
> 301635%7C0%7C0%7C636856478900947075&sdata=pg%2FZmo91Cxfji
> ESlBiR5shmsdxoYWslpfZeAXk5TV30%3D&reserved=0 ?
Ok. I'll post questions to binutils@sourceware.org
Thanks,
Peng.
>
>
> Segher
>
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