Re: Even numbered register pairs restriction on some instructions

[Paul Koning <paulkoning at comcast dot net>]

> On Aug 31, 2018, at 11:41 AM, Matthew Malcomson <matthew.malcomson@arm.com> wrote:
> 
> Hi there,
> 
> I'm looking into whether it's possible to require even numbered registers on
> modes that need more than one hard-register to represent them. But only in
> some cases.
> 
> The problem is the one mentioned explicitly here
> https://gcc.gnu.org/onlinedocs/gccint/Register-Classes.html about enforcing a
> requirement for a register pair to start with an even-numbered register.
> I can't use TARGET_HARD_REGNO_MODE_OK as suggested in that document because I'd
> like to allow register pairs starting with odd-numbered registers in general,
> but not in some specific cases.
> 
> From a comment in gcc/config/sparc/constraints.md above the constraint "U" it
> looks like there isn't a way to define such a constraint when using LRA, and I
> haven't found any hook that could do so but I'm hoping there's something I'm
> missing.

I think you can use pdp11 as an example, it does two things that are similar to what you're describing.

One is that it requires SImode to go into an even regno, and indicates that it uses two registers.  See TARGET_HARD_REGNO_MODE_OK and TARGET_HARD_REGNO_NREGS.

The other is that it has one instruction that wants an odd (!) register: 16 bit multiply.  Multiply is weird: if you give it an even destination register it produces a 32 bit result in that register pair, with an odd register number it produces a 16 bit result.  So pdp11.md defines both "mulhi3" and "mulsihi3" insns.  The latter has an SImode output so that uses the even numbered register, as I already described.  The former uses a machine-specific constraint "d".  That is defined in constraints.md to mean a register in class MUL_REGS.  pdp11.h defines that name and what registers it refers to, and pdp11.h does the reverse mapping (REGNO_REG_CLASS).

If you want even register numbers for some instructions but that's not tied to a specific type size (like SImode in my case), I think you'd want to use something analogous to the MUL_REGS thing I described.  Say, "EVEN_REGS".  REGNO_REG_CLASS would report even regnum to be in EVEN_REGS, odd in GENERAL_REGS.  The bitmaps for REG_CLASS_CONTENTS would show that EVEN_REGS contains only even numbered registers while GENERAL_REGS contains both odd and even.  And you'd defined a register constraint which matches EVEN_REGS.  Then the instructions where you want them would use that constraint.

	paul