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code-gen options for disabling multi-operand AArch64 and ARM instructions


Apologies if this isn't the right place for asking. For the problem
statement, I'll simply steal Ard's writeup [1]:

> KVM on ARM refuses to decode load/store instructions used to perform
> I/O to emulated devices, and instead relies on the exception syndrome
> information to describe the operand register, access size, etc. This
> is only possible for instructions that have a single input/output
> register (as opposed to ones that increment the offset register, or
> load/store pair instructions, etc). Otherwise, QEMU crashes with the
> following error
>   error: kvm run failed Function not implemented
>   [...]
>   QEMU: Terminated
> and KVM produces a warning such as the following in the kernel log
>   kvm [17646]: load/store instruction decoding not implemented
> GCC with LTO enabled will emit such instructions for Mmio[Read|Write]
> invocations performed in a loop, so we need to disable LTO [...]

We have a Red Hat Bugzilla about the (very likely) same issue [2].

Earlier, we had to work around the same on AArch64 too [3].

Would it be possible to introduce a dedicated -mXXX option, for ARM and
AArch64, that disabled the generation of such multi-operand

I note there are several similar instructions (for other architectures):
* -mno-multiple (ppc)
* -mno-fused-madd (ia64)
* -mno-mmx and a lot of friends (x86)

Obviously, if the feature request is deemed justified, we should provide
the exact family of instructions to disable. I'll leave that to others
on the CC list with more ARM/AArch64 expertise; I just wanted to get
this thread started. (Sorry if the option is already being requested
elsewhere; I admit I didn't search the GCC bugzilla.)



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