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Re: Re: Implementing TI mode (128-bit) and the 2nd pipeline for the MIPS R5900
- From: Liu Woon Yung <ysai187 at yahoo dot com>
- To: Richard Henderson <rth at redhat dot com>, "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Date: Sun, 27 Mar 2016 21:08:48 +0800
- Subject: Re: Re: Implementing TI mode (128-bit) and the 2nd pipeline for the MIPS R5900
- Authentication-results: sourceware.org; auth=none
- References: <56E055A2 dot 2030709 at redhat dot com>
Hi Richard,
On 10/3/2016 12:56 AM, Richard Henderson wrote:
Why do you believe that not using TImode precludes you implementing
any vector support? I don't think you need to touch TImode at all.
Just implement V16QImode, V8HImode and maybe V4SImode.
These modes can be special cased within mips_hard_regno_nregs and
mips_class_max_nregs to only consume one register.
Indeed, you are right! My original statements were the result of mixing
TI mode with the vector modes, which prevented me from indicating
support for 128-bit storage within mips_hard_regno_nregs and
mips_hard_regno_ok.
When I totally stripped off the broken support for TI mode, and made the
recommended changes to mips_hard_regno_nregs and mips_hard_regno_ok,
everything seems to be working fine now. Even argument passing and
return values.
I even got the inline memcpy to work with 16-byte copies by changing the
word type to vector integer for the the R5900.
Thank you!
Now, the only feature left unimplemented is support for the COP0 (FPU)
instructions (i.e. madda.s). I can't get GCC to emit them, but I'll
start another discussion in a different thread at a later time; I would
like to first get my facts right because I am not sure if it was even
supported by the SONY GCC releases.