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Re: Question about "instruction merge" pass when optimizing for size

> ________________________________________
> From: Jeff Law <>
> More important is to determine *why* we're getting these patterns.  In
> the IRA/LRA world, they should be a lot less common.

Yes I agree this phenomena seems more common after introducing LRA.

Though I was thinking that such a pass still maybe can be relevant.

Thinking hypothetically of an architecture, lets call it cortex-X,
assume this specific target type have an op-code for ADD with 5-operands.

Optimal code for

a = a + b + c + d

would be

addx Ra,Ra,Rb,Rc,Rd

where in the optimization process do we introduce the merging into this target type specific instruction.
Can the more generic IRA/LRA handle this?
And maybe patterns can appear across different BB, or somewhere that the normal optimizers have hard to find, or figure out?

Sorry if I'm ignorant, I don't know the internals of the different optimizers, but I'm trying to learn and understand how to come forward on this issue we have with code size currently.
(I tried to but some bugs on it also Bug 61578 and Bug 67213.)

Thanks and Kind Regards, Fredrik

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