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Question about LRA in aarch64_be-none-elf
- From: Kugan <kugan dot vivekanandarajah at linaro dot org>
- To: "gcc at gcc dot gnu dot org" <gcc at gcc dot gnu dot org>
- Cc: Vladimir Makarov <vmakarov at redhat dot com>
- Date: Sat, 07 Jun 2014 21:18:08 +1000
- Subject: Question about LRA in aarch64_be-none-elf
- Authentication-results: sourceware.org; auth=none
Hi All,
I am looking at a regression (in aarch64_be-none-elf-gcc -Og and
test-case attached) where a TImode register is assigned two DImode
values and then passed to the __multf3 as argument. When, the
intermediate pseudo(TImode) is assigned a FP_REG to hold this value, the
regression shows up. Difference in asm to the one working and not
working is below.
fmov d1, x20
fmov v1.d[1], x19
+ str q0, [x29, 64]
+ str x22, [x29, 64]
fmov d0, x21
- fmov v0.d[1], x22
bl __multf3
When LRA assigns one of the DImode value to TImode register, it spills
the TImode register into memory. Appends the DImode and then reloads (as
shown below in the dump). However, It is not setting up it in the right
place of TImode and due to that one of the moves becomes dead and
removed by dce. If I compile the test-case with
fno-dce, I get the following asm.
If I compile with -fno-dce.
fmov d1, x3
fmov v1.d[1], x19
str q0, [x29, 64]
str x19, [x29, 64]
ldr q0, [x29, 64]
fmov d0, x3
bl __addtf3
What is causing the LRA to generate moves like this?
Thanks,
Kugan
t.c.214r.reload
---------------
(insn 88 87 133 3 (clobber (reg:TI 32 v0 [orig:108 d+-8 ] [108])) t.c:11 -1
(nil))
---89, 134 and 91 stores
(insn 133 88 89 3 (set (mem/c:TI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S16 A128])
(reg:TI 32 v0 [orig:108 d+-8 ] [108])) t.c:11 37 {*movti_aarch64}
(nil))
(insn 89 133 134 3 (set (mem/c:DI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S8 A128])
(reg:DI 19 x19 [orig:102 d ] [102])) t.c:11 34 {*movdi_aarch64}
(nil))
(insn 134 89 90 3 (set (reg:TI 32 v0 [orig:108 d+-8 ] [108])
(mem/c:TI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S16 A128])) t.c:11 37
{*movti_aarch64}
(nil))
(insn 90 134 91 3 (set (reg:DI 32 v0 [orig:108 d ] [108])
(reg:DI 20 x20 [orig:105 d+8 ] [105])) t.c:11 34 {*movdi_aarch64}
(nil))
(insn 91 90 15 3 (set (reg:TF 32 v0)
(reg:TF 32 v0 [orig:108 d+-8 ] [108])) t.c:11 40 {*movtf_aarch64}
(nil))
(call_insn/u 15 91 129 3 (parallel [
(set (reg:TF 32 v0)
(call (mem:DI (symbol_ref:DI ("__addtf3") [flags 0x41])
[0 S8 A8])
(const_int 0 [0])))
(use (const_int 0 [0]))
(clobber (reg:DI 30 x30))
]) t.c:11 28 {*call_value_symbol}
(expr_list:REG_EH_REGION (const_int -2147483648 [0xffffffff80000000])
(nil))
(expr_list (use (reg:TF 33 v1))
(expr_list (use (reg:TF 32 v0))
(nil))))
t.c.228r.cprop_hardreg
----------------------
(insn 88 174 133 3 (clobber (reg:TI 32 v0 [orig:108 d+-8 ] [108])) t.c:11 -1
(nil))
(insn 133 88 89 3 (set (mem/c:TI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S16 A128])
(reg:TI 32 v0 [orig:108 d+-8 ] [108])) t.c:11 37 {*movti_aarch64}
(expr_list:REG_DEAD (reg:TI 32 v0 [orig:108 d+-8 ] [108])
(nil)))
(insn 89 133 134 3 (set (mem/c:DI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S8 A128])
(reg:DI 19 x19 [orig:102 d ] [102])) t.c:11 34 {*movdi_aarch64}
(nil))
(insn 134 89 90 3 (set (reg:TI 32 v0 [orig:108 d+-8 ] [108])
(mem/c:TI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S16 A128])) t.c:11 37
{*movti_aarch64}
(expr_list:REG_UNUSED (reg:TI 32 v0 [orig:108 d+-8 ] [108])
(nil)))
(insn 90 134 15 3 (set (reg:DI 32 v0 [orig:108 d ] [108])
(reg:DI 3 x3 [orig:105 d+8 ] [105])) t.c:11 34 {*movdi_aarch64}
(nil))
(call_insn/u 15 90 175 3 (parallel [
(set (reg:TF 32 v0)
(call (mem:DI (symbol_ref:DI ("__addtf3") [flags 0x41])
[0 S8 A8])
(const_int 0 [0])))
(use (const_int 0 [0]))
(clobber (reg:DI 30 x30))
]) t.c:11 28 {*call_value_symbol}
(expr_list:REG_DEAD (reg:TF 33 v1)
(expr_list:REG_EH_REGION (const_int -2147483648
[0xffffffff80000000])
(nil)))
(expr_list (use (reg:TF 33 v1))
(expr_list (use (reg:TF 32 v0))
(nil))))
t.c.229r.rtl_dce
---------------
(insn 88 174 133 3 (clobber (reg:TI 32 v0 [orig:108 d+-8 ] [108])) t.c:11 -1
(nil))
(insn 133 88 89 3 (set (mem/c:TI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S16 A128])
(reg:TI 32 v0 [orig:108 d+-8 ] [108])) t.c:11 37 {*movti_aarch64}
(expr_list:REG_DEAD (reg:TI 32 v0 [orig:108 d+-8 ] [108])
(nil)))
(insn 89 133 90 3 (set (mem/c:DI (plus:DI (reg/f:DI 29 x29)
(const_int 64 [0x40])) [0 %sfp+-16 S8 A128])
(reg:DI 19 x19 [orig:102 d ] [102])) t.c:11 34 {*movdi_aarch64}
(nil))
(insn 90 89 15 3 (set (reg:DI 32 v0 [orig:108 d ] [108])
(reg:DI 3 x3 [orig:105 d+8 ] [105])) t.c:11 34 {*movdi_aarch64}
(nil))
(call_insn/u 15 90 175 3 (parallel [
(set (reg:TF 32 v0)
(call (mem:DI (symbol_ref:DI ("__addtf3") [flags 0x41])
[0 S8 A8])
(const_int 0 [0])))
(use (const_int 0 [0]))
(clobber (reg:DI 30 x30))
]) t.c:11 28 {*call_value_symbol}
(expr_list:REG_DEAD (reg:TF 33 v1)
(expr_list:REG_EH_REGION (const_int -2147483648
[0xffffffff80000000])
(nil)))
(expr_list (use (reg:TF 33 v1))
(expr_list (use (reg:TF 32 v0))
(nil))))
long double
f (d, i)
long double d;
int i;
{
long double e;
d = -d;
e = d;
if (i == 1)
d *= 2;
d -= e * d;
d -= e * d;
d -= e * d;
d -= e * d;
d -= e * d;
return d;
}