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RE: [RFC, MIPS] Relax NaN rules


> From: Maciej W. Rozycki [macro@codesourcery.com]
> Sent: Friday, March 21, 2014 16:21
> To: Joseph S. Myers
> Cc: Rich Fuhler; Matthew Fortune; Richard Sandiford; dalias@aerifal.cx; Andrew Pinski (pinskia@gmail.com); gcc@gcc.gnu.org; Moore, Catherine (Catherine_Moore@mentor.com)
> Subject: RE: [RFC, MIPS] Relax NaN rules
>
>
> Coprocessor loads (LWC1/LDC1/MTC1/MTHC1/DMTC1) and stores
> (SWC1/SDC1/MFC1/MFHC1/DMFC1) are not arithmetic and never trap on any bit
> patterns.  I reckon GCC already takes advantage of this and stores
> integers temporarily in FPRs in some cases.
>
>  Maciej

Thanks Maciej, I blame it on the 387 - corrupted me for life...

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